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2-1 o single chip programma b le p e r ipheral f or microcontroller-based applications o wide operating v oltage range ? l- v ersions: 3.0 to 5.5 v olts ? others: 4.5 to 5.5 v olts o 19 individually configura b le i/o pins that can be used as ? microcontroller i/o po r t e xpansion ? programma b le address decoder ( p ad) i/o ? latched address output ? open drain or cmos o t wo programma b le arr a ys ( p ad a and p ad b) ? t otal of 40 product t e r ms and up to 16 inputs and 24 outputs ? address decoding up to 1 mb ? logic replacement of discrete p als o ?o glue?microcontroller chip-set ? built-in address latches f or multipl e x ed address/data b u s ? non-multipl e x ed address/data b us mode ? ale and reset (non-psd3xxl v ersions) pola r ity programma b le ? selecta b le modes f or read and w r ite control b us as rd/wr or r/w/e o 256k to 2 mbits of uv ep r om (2 mbit v ersion is sramless) ? configura b le as 32, 64, 128 or 256k x 8 or as 16, 32, 64 or 128k x 16 ? divides into 8 equal mappa b le b lo c ks f or optimi z ed mapping ? blo c k resolution is 4k x 8 or 2k x 16 (psd3x1) to 32k x 8 or 16k x 16 (psd3x4r) ? as f ast as 70 ns ep r om access tim e , including input latches and p ad address decoding. o 16 kbit static ram (no sram on psd3xxr v ersions) ? configura b le as 2k x 8 or as 1k x 16 ? as f ast as 70 ns sram access tim e , including input latches and p ad address decoding o built-in p age logic (psd3x2/3x3/3x4r) ? expands the mcu address space up to sixteen 1 mb pages o cmiser bit ? programma b le option to fu r ther reduce p o wer consumption o address/data t ra c k mode ? ena b les easy inter f ace to shared resources (mail b o x sram) with other microcontrollers or a host processor o built-in secu r ity ? lo c ks the d e vice and p ad decoding configuration key features programmable peripheral psd3xx family field-programmable microcontroller peripheral
psd3xx family 2-2 o computers (notebook and p o r ta b le pcs) fi x ed disk control, modem, imaging, laser printer control o t elecom m unications ? modem, cellular phon e , digital pbx, digital speech, f ax, digital signal processing o p o r ta b le indust r ia l equipment ? measurement inst r ument s , data recorders o medical inst r umentation ? monito r ing equipment, diagnostic t ools applications o moto r ola fami l y : m6805, m68hc11, m68hc16, m68000/10/20, m60008, m683xx o intel fami l y : 8031/8051, 8096/8098, 80186/88, 80196/98 o philips semiconducto r s: sc80c451, sc80552 o ti : sc80c451, tms320c14 o zilog: z8, z80, z180 o national: hpc16000, hpc46400 o e c helon: neu r on 3150 chip par tial listing of microcontrollers supported par t pld por ts eprom sram configuration memory c-miser securityinputs/ size size paging bit bitproduct ter ms PSD301 14/40 19 256 kb 16 kb x8 or x16 x x psd311 14/40 19 256 kb 16 kb x8 x x psd302 18/40 19 512 kb 16 kb x8 or x16 x x x psd312 18/40 19 512 kb 16 kb x8 x x x psd303 18/40 19 1 mb 16 kb x8 or x16 x x x psd313 18/40 19 1 mb 16 kb x8 x x x psd304r 18/40 19 2 mb x8 or x16 x x x psd314r 18/40 19 2 mb x8 x x x ps d3 xx family feature summary o a v aila b le in a v a r iety of p a c kaging ? 44 pin pldc c , cldc c , pqf p , tqf p , and cpga o simple me n u-d r i v en soft w are: configure the psd3xx on an ibm pc o psd3xx standard v ersions are e xcellent f or gene r al pu r pose applications o psd3xxr sramless v ersions result in l o wer cost o psd3xxl v ersions (3.0 to 5.5 v olt ope r ation) eliminate mixing and matching discrete l o w- v oltage pa r ts o psd3xxm mask-pro g ramma b le v ersions are ideal f or code-sta b l e , high- v olume l o w cost applications key features (cont.)
pr oduct revision data sheet revisions reason changes or iginal initial release psd3xx re vision a design changed f or impro v ed none psd3xx-a man uf actur ability and impro v ed margin to specification. psd3xx family 2-3 intr oduction the psd3xx f amily is the mar k et's first single-chip solution f or microcontroller-based applications where cr iter ia such as f ast time-to-mar k et, small f or m f actor , and lo w po w er consumption are essential. when combined in an 8- or 16-bit system, vir tually an y microcontroller (68hc11, 8031/8051, 80186, etc.) and the psd3xx de vice w or k together to create a v er y po w erful chip-set solution. the lo w-v oltage psd3xxl v ersions eliminate mixing and matching lo w v oltage specifications f or v ar ious discrete components . the y also pro vide all the required control and per ipher al elements needed in a microcontroller-based system with no e xter nal discrete ?lue?logic required. the psd3xx f amily comes complete with simple system softw are de v elopment tools f or interf acing the psd3xx with a microcontroller . hosted on an ibm p c platf or m or compatib le , the easy to use psdsoft softw are enab les the designer to quic kly configure the de vice and use it immediately . psd3xx standard v ersions are ideal f or gener al pur pose embedded control applications . psd3xxr (sram-less) v ersions are optimiz ed f or designs that either require no on-chip sram or require large off-chip srams f or data stor age . (sram-less v ersions w ere f or mer ly identified b y a ?1?suffix to the par t n umber .) psd3xxm mask-prog r ammab le v ersions deliv er the lo w est cost psd3xx solution. see the mask ed-psd order ing inf or mation chapter in this databook f or the mask-prog r ammab le psd3xxm order ing procedure . psd3xxl lo w-po w er v ersions oper ate do wn to 3.0 v olts and f eature standb y current of only 1 a typical. combinations of the abo v e v ersions are a v ailab le . see the order ing inf or mation section at the end of this data sheet. ref erences in this document to psd3xx v ersions include an y ?on-l ?products (e .g., psd3xx, psd3xxr, psd3xxm and psd3xxrm). ref erences to psd3xxr include an y sram-less product (psd3xxr, psd3xxrm, psd3xxrl and psd3xxrlm). ref erences to psd3xxm include psd3xxm, psd3xxrm, psd3xxlm, and psd3xxrlm products . ref erences to psd3xxl include psd3xxl, psd3xxlm, psd3xxrl and psd3xxrlm products . PSD301 is a registered tr ademar k of w af erscale integ r ation, inc. p al is a registered tr ademar k of adv anced micro de vices , inc. see page 1-15 f or gener al descr iption of product n umber ing. revisions
psd3xx family 2-4 p ro duc t description the psd3xx f amily inte g rates high per f o r mance user-configu r a b le b lo c ks of ep r om, sram, and pro g ramma b le logic. the major functional b lo c ks include t w o pro g ramma b le logic ar r a y s , p ad a and p ad b , 256k to 2mbit of ep r om, 16k bits of sram (no sram on psd3xxr v ersions), input latche s , and output po r t s . the psd3xx f amily is ideal f or applications requi r ing l o w p o wer and v e r y small f o r m f actor s . these include hard disk control, modem s , cellular telephone s , inst r umentation, computer pe r iphe r al s , milita r y and similar application s . the psd3xx f amily of f ers a unique single-chip solution f or microcontrollers that need: o i/o reconst r uction (microcontrollers lose at least t w o i/o po r ts when accessing e xte r nal resources). o more ep r om and sram than the microcontroller s inte r nal memo r y . o 3.3 v olt system ope r ation (psd3xxl v ersions). o chip-select, control, or latched address lines that are otherwise implemented discretel y . o an inter f ace to shared e xte r nal resource s . o expanded microcontroller address spac e . wsi s psd3xx f amily architecture (figure 1) can efficiently inter f ace with, and enhanc e , a n y l o w- v oltage 8- or 16-bit microcontroller system. this is the first solution that pr o vides microcontrollers with po r t e xpansion, latched addresse s , page logi c , two pro g ramma b le logic ar r a ys ( p ad a and p ad b), an inter f ace to shared resource s , 256k, 512k, 1m, or 2mbit ep r om, and 16k bit sram on a single chi p . the psd3xx f amily does not require a n y glue logic f or inter f acing to a n y 8- or 16-bit microcontrolle r . the 8051 microcontroller f amily can ta k e full ad v antage of the psd3xx s separate pro g ram and data address space s . users of the 68hcxx microcontroller f amily can change the functionality of the control signals and directly connect the r/w and e, or the r/w and ds signal s . (users of 16-bit microcontroller s , including the 80186, 8096, 80196 and 16xxx, can use the PSD301/302/303 in a 16-bit configu r ation). address and data b uses can be configured as sepa r ate or m ultipl e x ed, which e v er is required b y the host processo r . the fl e xibility of the psd3xx i/o po r ts pe r mits inter f acing to shared resource s . the arbit r ation can be controlled inte r nally b y p ad a output s . the user can assign the f oll o wing functions to these po r ts: standard i/o pin s , chip-select outputs from p ad a and p ad b , or latched address or m ultipl e x ed l o w-order address/data b yt e . this ena b les users to design add-on systems such as disk d r i v e s , modem s , etc., that easily inter f ace to the host b us ( e .g., ibm p c , scsi). the page register e xtends the accessi b le address space of ce r tain microcontrollers from 64 k to 1 m. there are 16 pages that can se r v e as base address inputs to the p a d , there b y enlarging the address space of 16 address line microcontrollers b y a f actor of 16.
psd3xx family 2-5 prog. port exp. port c pc0 pc2 es0 es1 es2 es3 es4 es5 es6 es7 prog. control signals a19/csi reset wr/r/w rd/e / ds ale/as bhe/psen pad a reset wr ale/as rd pad b a11?15 prog. port exp. port b pb0 pb7 prog. port exp. port a pa0 pa7 a19/csi reset ale/as a19/csi a8?10 wr rd ale/as l a t c h l a t c h ad8?d15 ad0?d7 d8?15 13 p.t. 27 p.t. page logic * logic in eprom 256kb to 2mb a16?18 cs8 cs10 cs0 cs7 sram 16k bit ** d0?7 rs0 a0?7 ad0?d7/d0?7 d8?15 csioport prog. chip configuration x8, x16 mux or non?ux busses security mode 16/8 mux csioport track mode selects p3?0 figure 1. psd3xx family architecture * * psd3x2/3x3/3x4r only . ** not a v ailab le on psd3xxr v ersions .
name t ype bhe/psen (psd30x i de vices) or psen (psd31x de vices i only) wr/v pp or r/w/v pp i rd/e/ds i (note 2) or rd/e i (note 3) description when the data b us width is 8 bits (cd a t a = 0), this pin is psen. in this mode , psen is the activ e lo w epr om read pulse . the sram and i/o por ts read signal is gener ated according to the descr iption of the wr/v pp or r/w and rd/e/ds pins . if the host processor is a member of the 8031 f amily , psen m ust be connected to the corresponding host pin. in other 8-bit host processors that do not ha v e a special epr om-only read strobe , psen should be tied to v cc . in this case , rd or e and r/w pro vide the read strobe f or the sram, i/o por ts , and epr om. when the data b us width is configured as 16 (cd a t a = 1), this pin is bhe. when bhe is lo w , data b us bits d8?15 are read from, or wr itten into , the psd3xx, depending on the oper ation being read or wr ite , respectiv ely . in prog r amming mode , this pin is pulsed betw een v pp and 0. the psen is the activ e lo w epr om read pulse . the sram and i/o por ts read signal is gener ated according to the descr iption of the wr/v pp or r/w , and rd/e pins . if the host processor is a member of the 8031 f amily , psen m ust be connected to the correspondinbg host pin. in other 8-bit host processors that do not ha v e a special epr om-only read strobe , psen should be tied to v cc . in this case , rd or e and r/w pro vide the read strobe f or the sram, i/o por ts , and epr om. in the oper ating mode this pin's function is wr (crr wr = 0) or r/w (crr wr = 1). when configured as r/w , the f ollo wing tab les summar iz e the read and wr ite oper ations (crr wr = 1): ceds = 0 ceds = 1 (note 2) r/w e r/w ds x 0 nop x 1 nop 0 1 wr ite 0 0 wr ite 1 1 read 1 0 read when configured as wr, a wr ite oper ation is e x ecuted dur ing an activ e lo w pulse . when configured as r/w , with r/w = 1 and e = 1, a read oper ation is e x ecuted; if r/w = 0 and e = 1, a wr ite oper ation is e x ecuted. in prog r amming mode , this pin m ust be tied to v pp v oltage . the pin function depends on the crr wr and ceds configur ation bits . if crr wr = 0, rd is an activ e lo w read pulse . when crr wr = 1, this pin and the r/w pin define the f ollo wing cycle type: if ceds = 0, e is an activ e high strobe . if ceds = 1, ds is an activ e lo w strobe . when configured as rd (crr wr = 0), this pin pro vides an activ e lo w rd strobe . when configured as e (crr wr = 1), this pin becomes an activ e high pulse , which, together with r/w defines the cycle type . then, if r/w = 1 and e = 1, a read oper ation is e x ecuted. if r/w = 0 and e = 1, a wr ite oper ation is e x ecuted. table 1. psd3xx pin descriptions legend: the i/o column ab bre viations are: i = input; i/o = input/output; p = po w er . no te : 1. all the configur ation bits mentioned in t ab le 1 appear in parentheses and are e xplained in the configur ation register section. 2. psd3x2/3x3/3x4r only . 3. psd3x1 only . psd3xx family 2-6
psd3xx family 2-7 description this pin has tw o configur ations . when it is csi (a19/csi = 0) and the pin is asser ted high, the de vice is deselected and po w ered do wn. (see t ab les 12 and 13 f or the chip state dur ing po w er-do wn mode .) if the pin is asser ted lo w , the chip is in nor mal oper ational mode . when it is configured as a19, (a19/csi = 1), this pin can be used as an additional input to the p ad . cadlog3 = 1 (ca td = 1 f or psd3x1) defines the pin as an address; cadlog3 = 0 (ca td = 0 f or psd3x1) defines it as a logic input. if it is an address , a19 can be latched with ale (caddhl t = 1) or be a tr ansparent logic input (caddhl t = 0). in this mode , there is no po w er-do wn capability . this user-prog r ammab le pin can be configured to reset on high le v el (creset = 1) or on lo w le v el (creset = 0). it should remain activ e f or at least 100 ns . see t ab les 10 and 11 and figure 11 f or reset details . in the m ultiple x ed modes , the ale pin functions as an address latch enab le or as an address strobe and can be configured as an activ e high or activ e lo w signal. the ale or as tr ailing edge latches lines ad15/a15?d0/a0 and a16?19 in 16-bit mode (ad7/a7?d0/a0 and a16?19 in 8-bit mode) and bhe, depending on the psd3xx configur ation. see t ab le 8. in the non-m ultiple x ed modes (psd3x2/3x3), it can be used as a gener al-pur pose logic input to the p ad . p a7? a0 is an 8-bit por t that can be configured to tr ac k ad7/a7?d0/a0 from the input (cp af2 = 1). otherwise (cp af2 = 0), each bit can be configured separ ately as an i/o or lo w er-order latched address line . when configured as an i/o (cp af1 = 0), the direction of the pin is defined b y its direction bit, which resides in the direction register . if a pin is an i/o output, its data bit (which resides in the data register) comes out. when it is configured as a lo w-order address line (cp af1 =1), a7?0 can be made the corresponding output through this por t (e .g., p a6 can be configured to be the a6 address line). each por t bit can be a cmos output (cp a cod = 0) or an open dr ain output (cp a cod = 1). when the chip is in non-m ultiple x ed mode (caddra t = 0), the por t becomes the data b us lines (d0?7). see figure 4. pb7?b0 is an 8-bit por t f or which each bit can be configured as an i/o (cpbf = 1) or chip-select output (cpbf = 0). each por t bit can be a cmos output (cpbcod = 0) or an open dr ain output (cpbcod = 1). when configured as an i/o , the direction of the pin is defined b y its direction bit, which resides in the direction register . if a pin is an i/o output, its data (which resides in the data register) comes out. when configured as a chip-select output, cs0?s3 are a function of up to f our product ter ms of the inputs to the p ad b; cs 4 cs7 then are each a function of up to tw o product ter ms . on the PSD301/302/303, when the chip is in non-m ultiple x ed mode (caddra t = 0) and the data b us width is 16 (cd a t a = 1), the por t becomes the data b us (d8?15). see figure 6. table 1. psd3xx pin descriptions (cont.) name t ype a1 9 / csi i reset i ale or i as p a7 p a6 p a5 p a4 i/o p a3 p a2 p a1 p a0 pb7 pb6 pb5 pb4 i/o pb3 pb2 pb1 pb0
psd3xx family 2-8 name t ype pc0 pc1 i/o pc2 ad0/a0 ad1/a1 ad2/a2 ad3/a3 i/o ad4/a4 ad5/a5 ad6/a6 ad7/a7 ad8/a8 ad9/a9 ad10/a10 ad11/a11 ad12/a12 i/o ad13/a13 ad14/a14 ad15/a15 gnd p v cc p description this is a 3-bit por t f or which each bit is configur ab le as a p ad a and b input or output. when configured as an input (cpcf = 0),a bit individually becomes an address (cadlog = 1 f or psd3x2/3x3, ca td = 1 f or psd3x1) or a logic input (cadlog = 0 f or psd3x2/3x3, ca td = 0 f or psd3x1). the addresses can be latched with ale (caddhl t = 1) or be tr ansparent inputs to the p ads (caddhl t = 0). when a pin is configured as an output (cpcf = 1), it is a function of one product ter m of all p ad inputs . see figure 7. in m ultiple x ed mode , these pins are the m ultiple x ed lo w-order address/data b yte . after ale latches the addresses , these pins input or output data, depending on the settings of the rd/e (rd/e/ds on the psd302/312/303/313), wr/v pp or r/w , and bhe/psen pins . in non-m ultiple x ed mode , these pins are the lo w-order address input. in 16-bit m ultiple x ed mode , these pins are the m ultiple x ed high-order address/data b yte . after ale latches the addresses , these pins input or output data, depending on the settings of the rd/e or rd/e/ds , wr/v pp or r/w , and bhe/psen pins . in all other modes , these pins are the high-order address input. v ss (g round) pin. supply v oltage input. table 1. psd3xx pin descriptions (cont.)
psd3xx family 2-9 operating modes the psd3xx s f our oper ating modes enab le it to interf ace directly to 8- and 16-bit microcontrollers with m ultiple x ed and non-m ultiple x ed address/data b uses . these oper ating modes are: o multiple x ed 8-bit address/data b us o multiple x ed 16-bit address/data b us (psd30x) o non-m ultiple x ed address/data, 8-bit data b us o non-m ultiple x ed 16-bit address/data b us (psd30x) multiplexed 8-bit addres s / data bus this mode is used to interf ace to microcontrollers with an 8-bit data b us and a 16-bit or larger address b us . the address/data b us (ad0/a0?d7/a7) is bi-directional and per mits the latching of the address when the ale signal is activ e . on the same pins , the data is read from or wr itten to the de vice; this depends on the state of the rd/e or rd/e/ds pin, bhe/psen or psen pin and wr/v pp or r/w pins . the high-order address/data b us (ad8/a8?d15/a15) contains the high-order address b us b yte . p or ts a and b can be configured as in t ab le 2. multiplexed 16-bit addres s / data bus this mode is used to interf ace to microcontrollers with a 16-bit data b us and a 16-bit or larger address b us . the lo w-order address/data b us (ad0/a0?d7/a7) is bi-directional and per mits the latching of the address when the ale signal is activ e . on the same pins , the data is read from or wr itten to the de vice; this depends on the state of the rd/e/ds , bhe/psen, and wr/v pp or r/w pins . the high-order address/data b us (ad8/a8?d15/a15) is bi-directional and per mits latching of the high-order address when the ale signal is activ e on the same pins . the high-order data b us is read from or wr itten to the de vice , depending on the state of the rd/e/ds , bhe/psen, and wr/v pp or r/w pins . p or ts a and b can be configured as in t ab le 2. non-multiplexed addres s / data, 8-bit data bus this mode is used to interf ace to non-m ultiple x ed 8-bit microcontrollers with an 8-bit data b us and a 16-bit or larger address b us . the lo w-order address/data b us (ad0/a0?d7/a7) is the lo w-order address input b us . the high-order address/data b us (ad8/a8?d15/a15) (a8?15 on the psd31x) is the high-order address b us b yte . p or t a is the lo w-order data b us . p or t b can be configured as sho wn in t ab le 2. non-multiplexed addres s / data, 16-bit data bus this mode is used to interf ace to non-m ultiple x ed 16-bit microcontrollers with a 16-bit data b us and a 16-bit or larger address b us . the lo w-order address/data b us (ad0/a0?d7/a7) is the lo w-order address input b us . the high-order address/data b us (ad8/a8?d15/a15) is the high-order address b us b yte . p or t a is the lo w-order data b us . p or t b is the high-order data b us . t ab le 2 summar iz es the eff ect of the diff erent oper ating modes on por ts a, b , and the address/data pins . the configur ation of p or t c is independent of the f our oper ating modes .
psd3xx family 2-10 legend: ad8?d15 = addresses a8?15 m ultiple x ed with data lines d8?15. ad0?d7 = addresses a0?7 m ultiple x ed with data lines d0?7. * = ds is a v ailab le on psd3x2/3x3/3x4r only . figure 2a. psd3xx port configurations (x 8 / x16) ad8 ad15 a8 a15 ad0 ad7 ad0 ad7 ale bhe / psen r / w or wr / v pp rd / e / ds * a19/csi reset i / o or cs0 cs7 a19/csi r / w or wr / v pp bhe / psen i / o or cs0 cs7 i / o or cs0 cs7 a16 a18 or cs8 cs10 a16 a18 or cs8 cs10 pa pb pc ale pa pb pc i / o or a0 a7 or ad0 ad7 i / o or a0 a7 or ad0 ad7 reset a8 a15 d8 ?15 a0 a7 ale bhe / psen r / w or wr / v pp rd / e / ds * a19/csi reset a16 a18 or cs8 cs10 pa pb pc d0 d7 a8 a15 a0 a7 ale bhe / psen r / w or wr / v pp rd / e / ds * a19/csi reset a16 a18 or cs8 cs10 pa pb pc d0 d7 rd / e / ds * a8 a15 ad0 ad7 ale psen r / w or wr / v pp rd / e / ds * a19 / csi reset i / o or cs0 cs7 a16 a18 or cs8 cs10 pa pb pc i / o or a0 a7 or ad0 ad7 a8 a15 a0 a7 ale psen r / w or wr / v pp rd / e / ds * a19/csi reset i / o or cs0 cs7 a16 a18 or cs8 cs10 pa pb pc d0 d7 figure 2b. psd31x port configurations (x8 only) 2. configured f or m ultiple x ed 8-bit address/data b us . 1. configured f or m ultiple x ed 16-bit address/data b us . 3. configured f or non-m ultiple x ed 16-bit address/data b us . 4. configured f or non-m ultiple x ed 8-bit address/data b us . 1. configured f or m ultiple x ed 8-bit address/data b us . 2. configured f or non-m ultiple x ed 8-bit address/data b us .
psd3xx family 2-11 programmable address decoder (pad) the psd3xx consists of tw o prog r ammab le arr a ys ref erred to as p ad a and p ad b (figure 3). p ad a is used to gener ate chip select signals der iv ed from the input address to the inter nal epr om b loc ks , sram, i/o por ts , and t r ac k mode signals . all its i/o functions are listed in t ab le 3 and sho wn in figure 3. p ad b outputs to p or ts b and c f or off-chip usage . p ad b can also be used to e xtend the decoding to select e xter nal de vices or as a r andom logic replacement. the input b us to both p ad a and p ad b is the same . by using the psdsoft de v elopment t ools softw are , each prog r ammab le bit in the p ad arr a y can ha v e one of three logic states of 0, 1, and don? care (x). in a user s logic design, both p ads can share the same inputs , using the x f or input signals that are not supposed to aff ect other functions . the p ads use reprog r ammab le cmos epr om technology and can be prog r ammed and er ased (if using windo w ed pac kages) b y the user . multiplexed addr es s / data non-multiplexed addr es s / data 8-bit data bus i/o or lo w-order address p or t a lines or lo w-order m ultiple x ed d0?7 data b us b yte address/data b yte p or t b i/o and/or cs0?s7 i/o and/or cs0?s7 ad0/a0?d7/a7 lo w-order m ultiple x ed address/data b yte lo w-order address b us b yte ad8/a8?d15/a15 high-order m ultiple x ed high-order address b us b yte address data b yte 16-bit data bus i/o or lo w-order address p or t a lines or lo w-order m ultiple x ed lo w-order data b us b yte address/data b yte p or t b i/o and/or cs0?s7 high-order data b us b yte ad0/a0?d7/a7 lo w-order m ultiple x ed address/data b yte lo w-order address b us b yte ad8/a8?d15/a15 high-order m ultiple x ed address/data b yte high-order address b us b yte table 2. psd30x bus and port configuration options multiplexed addr es s / data non-multiplexed addr es s / data 8-bit data bus i/o or lo w-order address p or t a lines or lo w-order m ultiple x ed d0?7 data b us b yte address/data b yte p or t b i/o and/or cs0?s7 i/o and/or cs0?s7 ad0/a0?d7/a7 lo w-order m ultiple x ed address/data b yte lo w-order address b us b yte a8?15 high-order address b us b yte high-order address b us b yte table 2a. psd31x bus and port configuration options
figure 3. pad description ale or as wr or r/w a19 a18 a17 a16 a15 a14 a13 a12 a11 es0 es1 es2 es3 es4 es5 es6 es7 rs0 csioport csadin csadout1 csadout2 cs0/pb0 cs1/pb1 cs2/pb2 cs3/pb3 cs4/pb4 cs5/pb5 cs6/pb6 cs7/pb7 cs8/pc0 cs9/pc1 cs10/pc2 rd/e/ds 8 eprom block select lines csi reset sram block select * track mode control signals p 0 p 1 p 2 p 3 i/o base address pad b pad a no tes: 4. csi is a po w er-do wn signal. when high, the p ad is in stand-b y mode and all its outputs become non-activ e . see t ab les 12 and 13. 5. reset deselects all p ad output signals . see t ab les 10 and 11. 6. a18, a17, and a16 are inter nally m ultiple x ed with cs10, cs9, and cs8, respectiv ely . either a18 or cs10, a17 or cs9, and a16 or cs8 can be routed to the e xter nal pins of p or t c . p or t c can be configured as either input or output. 7. p 0 ? 3 are not included on psd3x1 de vices . 8. ds is not a v ailab le on psd3x1 de vices . psd3xx family 2-12 * not a v ailab le on psd3xxr v ersions .
psd3xx family 2-13 function p ad a and p ad b inputs in csi mode (when high), p ad deselects all of its outputs and enters a a19/csi po w er-do wn mode (see t ab les 12 and 13). in a19 mode , it is another input to the p ad . a16?18 these are gener al pur pose inputs from p or t c . see figure 3, note 6. a11?15 these are address inputs . p0?3 these are page n umber inputs (f or the psd302/312/303/313 only). rd/e/ds this is the read pulse or enab le strobe input. (note 10) wr or r/w this is the wr ite pulse or r/w select signal. ale this is the ale input to the chip . reset this deselects all outputs from the p ad; it can not be used in product ter m equations . see t ab les 10 and 11 and figure 11. p ad a outputs these are inter nal chip-selects to the 8 epr om banks . each bank can es0?s7 be located on an y boundar y that is a function of one product ter m of the p ad address inputs . rs0 this is an inter nal chip-select to the sram. its base address location is a function of one ter m of the p ad address inputs . (not a v ailab le on psd3xxr v ersions). this inter nal chip-select selects the i/o por ts . it can be placed on an y csiopor t boundar y that is a function of one product ter m of the p ad inputs . see t ab les 6 and 7. this inter nal chip-select, when p or t a is configured as a lo w-order address/data b us in the tr ac k mode (cp af2 = 1), controls the input direction of p or t a. csadin is gated e xter nally to the p ad b y the csadin inter nal read signal. when csadin and a read oper ation are activ e , data presented on p or t a flo ws out of ad0/a0?d7/a7. this chip-select can be placed on an y boundar y that is a function of one product ter m of the p ad inputs . see figure 5. this inter nal chip-select, when p or t a is configured as a lo w-order address/data b us in tr ac k mode (cp af2 = 1), controls the output direction of p or t a. csadout1 is gated e xter nally to the p ad b y the ale csadout1 signal. when csadout1 and the ale signal are activ e , the address presented on ad0/a0?d7/a7 flo ws out of p or t a. this chip-select can be placed on an y boundar y that is a function of one product ter m of the p ad inputs . see figure 5. this inter nal chip-select, when p or t a is configured as a lo w-order address/data b us in the tr ac k mode (cp af2 = 1), controls the output direction of p or t a. csadout2 m ust include the wr ite-cycle control csadout2 signals as par t of its product ter m. when csadout2 is activ e , the data presented on ad0/a0?d7/a7 flo ws out of p or t a. this chip-select can be placed on an y boundar y that is a function of one product ter m of the p ad inputs . see figure 5. p ad b outputs cs 0 cs3 these chip-select outputs can be routed through p or t b . each of them is a function of up to f our product ter ms of the p ad inputs . cs 4 cs7 these chip-select outputs can be routed through p or t b . each of them is a function of up to tw o product ter ms of the p ad inputs . cs 8 cs10 these chip-select outputs can be routed through p or t c . see figure 3, note 6. each of them is a function of one product ter m of the p ad inputs . table 3. psd3xx pad a and pad b functions
psd3xx family 2-14 use this bit t o cd a t a set the data b us width to 8 or 16 bits (psd30x only). caddrd a t set the address/data b uses to m ultiple x ed or non-m ultiple x ed mode . ceds deter mine the polar ity and functionality of read and wr ite . (note 10) ca19/csi set a19/csi to csi (po w er-do wn) or a19 input. cale set the ale polar ity . cp af2 set p or t a either to tr ac k the lo w-order b yte of the address/data m ultiple x ed b us or to select the i/o or address option. csecurity set the secur ity on or off (a secured par t can not be duplicated). creset set the reset polar ity . comb/sep set psen and rd f or combined or separ ate address spaces (see figures 9 and 10). cp af1 configure each pin of p or t a in m ultiple x ed mode to be an i/o or (8 bits) address out. cp a cod configure each pin of p or t a as an open dr ain or activ e cmos (8 bits) pull-up output. cpbf configure each pin of p or t b as an i/o or a chip-select output . (8 bits) cpbcod configure each pin of p or t b as an open dr ain or activ e cmos (8 bits) pull-up output. cpcf configure each pin of p or t c as an address input or a chip-select output. (3 bits) caddhl t configure pins a16 ?a19 to go through a latch or to ha v e their latch tr ansparent. cadlog configure a16 ?a19 individually as logic or address inputs . (note 10) (4 bits) ca td configure pins a16?19 as p ad logic inputs or high-order address inputs (note 9). clo t deter mine in non-m ultiple x ed mode if address inputs are tr ansparent or latched (note 10). crr wr set the rd/e and wr/v pp or r/w pins to rd and wr pulse , or to e strobe and r/w status (note 9). crr wr configure the polar ity and control methods of read and wr ite cycles . (note 10) cmiser controls the lo w er-po w er mode . table 4. psd3xx non-volatile configuration bits configuration bits the configur ation bits sho wn in t ab le 4 are non-v olatile cells that let the user set the de vice , i/o , and control functions to the proper oper ational mode . t ab le 5 lists all configur ation bits . the configur ation bits are prog r ammed and v er ified dur ing the prog r amming phase . in oper ational mode , the y are not accessib le . these tab les are f or inf or mation only since to implement to a specific mode , the psdsoft de v elopment softw are will automatically set the configur ation bits b y using simple inter activ e men us . no tes: 9. psd3x1 only . 10. psd302/312/303/313/304r/314r only . this data sheet pro vides a complete listing of the function of each configur ation bit in all control registers . in gener al, y ou will not need to be concer ned about the details of most of these bits . the de v elopment softw are will set the bits automatically using inf or mation from y our design files .
2-15 psd3xx family configuration no. function bits of bits cd a t a 8-bit or 16-bit data bus width (note 13) 1 cd a t a = 0 eight bits cd a t a = 1 sixteen bits address/d a t a multiple x ed (separ ate b uses) caddrd a t 1 caddrd a t = 0, non-m ultiple x ed caddrd a t = 1, m ultiple x ed a19 or csi ca19/csi 1 ca19/csi = 0, enab le po w er-do wn ca19/csi = 1, enab le a19 input to p ad activ e high or activ e lo w cale 1 cale = 0, activ e high cale = 1, activ e lo w activ e high or activ e lo w creset 1 creset = 0, activ e lo w reset signal creset = 1, activ e high reset signal combined or separ ate address space comb/sep 1 f or sram and epr om 0 = combined, 1 = separ ate p or t a i/os or a0?7 cp af1 8 cp af1 = 0, p or t a pin = i/o cp af1 = 1, p or t a pin = a0 ?a7 p or t a ad0?d7 (address/data m ultiple x ed b us) cp af2 1 cp af2 = 0, address or i/o on p or t a (according to cp af1) cp af2 = 1, address/data m ultiple x ed on p or t a (tr ac k mode) a16?19 address or logic inputs ca td 1 ca td = 0, logic inputs (note 15) ca td = 1, address inputs a16?19 t r ansparent or latched caddhl t 1 caddhl t = 0, address latch tr ansparent caddhl t = 1, address latched (ale dependent) security on/off csecurity 1 csecurity = 0, off csecurity = 1, on a0?15 address inputs are tr ansparent or clo t 1 ale-dependent in non-m ultiple x ed modes (note 14) clo t = 0, tr ansparent clo t = 1, ale-dependent deter mine the polar ity and control methods of read and crr wr wr ite cycles . ceds 2 ceds crr wr (note 14) 0 0 rd and wr activ e lo w pulses 0 1 r/w status and high e pulse 1 1 r/w status and lo w ds pulse crr wr 1 crr wr = 0, rd and wr activ e lo w strobes (note 15) crr wr = 1, r/w status and e activ e high pulse p or t a cmos or open dr ain output cp a cod 8 cp a cod = 0, cmos output cp a cod = 1, open-dr ain output t able 5. psd3xx configuration bit s 11,12
psd3xx family 2-16 psd3xx family the psd3xx has three i/o por ts (p or ts a, b , and c) that are configur ab le at the bit le v el. this per mits g reat fle xibility and a high deg ree of customization f or specific applications . the f ollo wing is a descr iption of each por t. figure 4 sho ws the pin str ucture of p or t a. por t a in multiplexed addr es s / data mode the def ault configur ation of p or t a is i/o . in this mode , e v er y pin can be set as an input or output b y wr iting into the respectiv e pin s direction flip flop (dir ff , in figure 4). as an output, the pin le v el can be controlled b y wr iting into the respectiv e pin s data flip flop (dff , in figure 4). when dir ff = 1, the pin is configured as an output. when dir ff = 0, the pin is configured as an input. the controller can read the dir ff bits b y accessing the read dir register ; it can read the dff bits b y accessing the read d a t a register . p or t a pin le v els can be read b y accessing the read pin register . individual pins can be configured as cmos or open dr ain outputs . open dr ain pins require e xter nal pull-up resistors . f or addressing inf or mation, ref er to t ab les 6 and 7. alter nativ ely , each bit of p or t a can be configured as a lo w-order latched address b us bit. the address is pro vided b y the por t address latch, which latches the address on the tr ailing edge of ale. p a0? a7 can become a0?7, respectiv ely . this f eature enab les the user gener ate lo w-order address bits to access e xter nal per ipher als or memor y that require se v er al lo w-order address lines . another mode of p or t a, i.e ., t r ac k mode (cp af2 = 1) sets the entire por t to tr ac k the inputs ad0/a0?d7/a7, depending on specific address r anges defined b y the p ad s csadin, csadout1, and csadout2 signals . this f eature lets the user interf ace the microcontroller to shared e xter nal resources without requir ing e xter nal b uff ers and decoders . in this mode , the por t is eff ectiv ely a bi-directional b uff er . the direction is controlled b y using the input signals ale, rd/e or rd/e/ds , wr/v pp or r/w , and the inter nal p ad outputs csadout1, csadout2 and csadin (see figure 5). when csadout1 and ale are tr ue , the address on the input ad0/a0?d7/a7 pins is output through p or t a. (carefully chec k the gener ation of csadout1, and ensure that it is stab le dur ing the ale pulse . when csadout2 is activ e , a wr ite oper ation is perf or med (see note to figure 5). the data on the input ad0/a0?d7/a7 pins flo ws out through p or t a. when csadin and a read oper ation is perf or med (depending on the mode of the rd/e or rd/e/ds , and wr/v pp or r/w pins), the data on p or t a flo ws out through the ad0/a0?d7/a7 pins . in this oper ational mode , p or t a is tr i-stated when none of the abo v e-mentioned three conditions e xist. por t functions configuration no. function bits of bits p or t b is i/o or cs0?cs7 cpbf 8 cpbf = 0, p or t b pin is cs0 ?cs7 cpbf = 1, p or t b pin is i/o p or t b cmos or open dr ain cpbcod 8 cpbcod = 0, cmos output cpbcod = 1, open-dr ain output p or t c a16?18 or cs8?s10 cpcf 3 cpcf = 0, p or t c pin is a16?18 cpcf = 1, p or t c pin is cs8?s10 cadlog p or t c: a16?19 address or logic input (note 14) 4 cadlog = 0, p or t c pin or a19/csi is logic input cadlog = 1, p or t c pin or a19/csi is address input cmiser 1 def ault: cmiser = 0 cmiser = 1, lo w er-po w er mode t able 5. psd3xx configuration bits (cont.) no tes: 11. the psd de v elopment softw are will guide the user to the proper configur ation choice . 12. in an unprog r ammed or er ased par t, all configur ation bits are 0. 13. psd30x only . 14. psd3x2/3x3 only . 15. psd3x1 only .
psd3xx family 2-17 figur e 5. por t a t rack mode no te: 17. the e xpression f or csadout2 m ust include the f ollo wing wr ite oper ation cycle signals: f or crr wr = 0, csadout2 m ust include wr = 0. f or crr wr = 1, csadout2 m ust include e = 1 and r/w = 0. internal read csadin internal ale pa0 pa7 a11 a15 a16 a19 ad8 ad15 csadout1 csadout2 (17) ale or as ad0 ?d7 rd / e wr or r / w control decoder latch pad i o figur e 4. por t a pin str uctur e no te: 16. cmos/od deter mines whether the output is open dr ain or cmos . read pin port a pin enable addr out adi / di read data write data ale read dir write dir reset ck d r g d r d ck r cmos / od (16) i n t e r n a l a d d r / d a t a b u s a d 0 / a d 7 dff latch dir ff control mux
psd3xx family 2-18 por t a in non-multiplexed addr es s / data mode in this mode , p or t a becomes the lo w order data b us b yte of the chip . when reading an inter nal location, data is presented on p or t a pins . when wr iting to an inter nal location, data present on p or t a pins is wr itten to that location. por t b in multiplexed addr es s / data and in 8-bit non-multiplexed modes the def ault configur ation of p or t b is i/o . in this mode , e v er y pin can be set as an input or output b y wr iting into the respectiv e pin s direction flip flop (dir ff , in figure 6). as an output, the pin le v el can be controlled b y wr iting into the respectiv e pin s data flip flop (dff , in figure 6). when dir ff = 1, the pin is configured as an output. when dir ff = 0, the pin is configured as an input. the controller can read the dir ff bits b y accessing the read dir register ; it can read the dff bits b y accessing the read d a t a register . p or t b pin le v els can be read b y accessing the read pin register . individual pins can be configured as cmos or open dr ain outputs . open dr ain pins require e xter nal pull-up resistors . f or addressing inf or mation, ref er to t ab les 6 and 7. alter nately , each bit of p or t b can be configured to pro vide a chip-select output signal from p ad b . pb0?b7 can pro vide cs0?s7, respectiv ely . each of the signals cs0?s3 is compr ised of f our product ter ms .thus , up to f our anded e xpressions can be ored while der iving an y of these signals . each of the signals cs4?s7 is compr ised of tw o product ter ms . thus , up to tw o anded e xpressions can be ored while der iving an y of these signals . por t b in 16-bit non-multiplexed addr es s / data mode (psd30x) in this mode , p or t b becomes the high-order data b us b yte of the chip . when reading an inter nal high-order data b us b yte location, the data is presented on p or t b pins . when wr iting to an inter nal high-order data b us b yte location, data present on p or t b is wr itten to that location. see t ab le 9. accessing the i/o por t registers t ab les 6 and 7 sho w the offset v alues with the respect to the base address defined b y the csiopor t . the y let the user access the corresponding registers . por t c in all modes each pin of p or t c (sho wn in figure 7) can be configured as an input to p ad a and p ad b or output from p ad b . as inputs , the pins are named a16?18. although the pins are giv en names of the high-order address b us , the y can be used f or an y other address lines or logic inputs to p ad a and p ad b . f or e xample , a8?10 can also be connected to those pins , impro ving the boundar ies of cs0?s7 resolution to 256 b ytes . as inputs , the y can be individually configured to be logic or address inputs . a logic input uses the p ad only f or boolean equations that are implemented in an y or all of the cs0?s10 p ad b outputs . p or t c addresses can be prog r ammed to latch the inputs b y the tr ailing edge ale or to be tr ansparent. alter nately , pc0?c2 can become cs8?s10 outputs , respectiv ely , pro viding the user with more e xter nal chip-select p ad outputs . each of the signals cs8?s10 is compr ised of one product ter m. al e / as and a 0 a15 in non-multiplexed modes (psd3x 2 / 3x3) in non-m ultiple x ed modes , a 0 a15 are address inputs only and can become tr ansparent (clo t = 0) or ale dependent (clo t = 1). in tr ansparent mode , the ale/as pin can be used as an additional logic input to the p ads . the non-m ultiple x ed ale dependent mode is useful in applications f or which the host processor has a m ultiple x address/data b us and ad0/a0?d7/a7 are not m ultiple x ed with a0?7 b ut r ather are m ultiple x ed with other address lines . in these applications , p or t a ser v es as a data b us and each of its pins can be directly connected to the corresponding host s m ultiple x ed pin, where that data bit is e xpected. (see t ab le 8.) por t functions (cont.) psd3xx family
psd3xx family 2-19 psd3xx family no tes: 19. when the data b us width is 16, p or t b registers can only be accessed if the bhe signal is lo w . 20. i/o p or ts a and b are still b yte-addressab le , as sho wn in t ab le 6. f or i/o p or t b register access , bhe m ust be lo w . register name w or d size access of the i/o por t registers of fset fr om the csiopor t pin register of p or ts b and a + 2 (accessib le dur ing read oper ation only) direction register of p or ts b and a + 4 data register of p or ts b and a + 6 t able 7. i/o por t addr esses in a 16-bit data bus mod e 19,20 (psd30x) figur e 6. por t b pin str uctur e read pin read data port b pin cmos/od (18) out write data ck d r dff enable mux di csi control dir ff d ck r write dir reset read dir i n t e r n a l i n t e r n a l c s o u t d a t a b u s b u s c s 0 7 d 8 d 1 5 register name byte size access of the i/o por t registers of fset fr om the csiopor t pin register of p or t a + 2 (accessib le dur ing read oper ation only) direction register of p or t a + 4 data register of p or t a + 6 pin register of p or t b + 3 (accessib le dur ing read oper ation only) direction register of p or t b + 5 data register of p or t b + 7 p age register +18 t able 6. i/o por t addr esses in an 8-bit data bus mode no te: 18. cmos/od deter mines whether the output is open dr ain or cmos .
figur e 7. por t c str uctur e cs8 (output line) from pad to pad a16 cs9 (output line) from pad to pad a17 cs10 (output line) from pad to pad a18 ale address indicator (note 21) to eprom pc0 pc1 pc2 cadlog0 conf. bit address latch cadlog1 conf. bit address latch cpcf1 conf. bit cadlog2 conf. bit address latch caddhlt configuration bit: latch or transparent control cpcf2 conf. bit cpcf0 conf. bit psd3xx family 2-20 no tes: 21. the caddhl t configur ation bit deter mines if a18?16 are tr ansparent via the latch, or if the y m ust be latched b y the tr ailing edge of the ale strobe . 22. psd3x2/3x3/3x4r: individual pins can be configured independently as address or logic inputs (cadlog, bits 0?). psd3x1: all p or t c pins are either address or logic inputs (ca td).
psd3xx family 2-21 sram eprom the epr om has 8 banks of memor y . each bank can be placed in an y address location b y prog r amming the p ad . bank0?ank7 is selected b y p ad outputs es0?s7, respectiv ely . each psd3xx de vice has 16k bits of sram (e xcept the psd3xxr v ersions which ha v e no sram). depending on the configur ation of the data b us , the sram organization can be 2k x 8 (8-bit data b us) or 1k x 16 (16-bit data b us). the sram is selected b y the rs0 output of the p ad . a1 6 a19 inputs if one or more of the pins pc0, pc1 pc2 and csi/a19 are configured as inputs , the configur ation bits caddhl t and ca td define their functionality inside the par t. caddhl t deter mines if these inputs are to be latched b y the tr ailing edge of the ale or as signal (caddhl t = 1), or enab led into the psd3xx at all times (caddhl t = 0, tr ansparent mode). ca td deter mines whether these lines are high-order address lines , that tak e par t in the der iv ation of epr om select signals inside the chip (ca td = 1), or logic input lines that ha v e no impact on memor y or i/o selections (ca td = 0). logic input lines typically par ticipate in the boolean e xpressions implemented in the p ad b . un used input pins should be tied to v cc or gnd . eprom eprom eprom bank device size ar chitectur e ar chitectur e (8 ea) x8 x16 x8 x16 PSD301 256kb 32k x 8 16k x 16 4k x 8 2k x 16 psd311 256kb 32k x 8 4k x 8 psd302 512kb 64k x 8 32k x 16 8k x 8 4k x 16 psd312 512kb 64k x 8 8k x 8 psd303 1mb 128k x 8 64k x 16 16k x 8 8k x 16 psd313 1mb 128k x 8 16k x 8 psd304r 2mb 256k x 8 128k x 16 32k x 8 16k x 8 psd314r 2mb 256k x 8 32k x 8
signal configuration configuration signal latch name bits mode status cd a t a , caddrd a t , clo t = 0 8-bit data, t r ansparent cd a t a, caddrd a t = 0, clo t = 1 non-m ultiple x ed ale dependent cd a t a = 1, caddrd a t , clo t = 0 16-bit data, t r ansparent ad8/a8 cd a t a = 1, caddrd a t = 0, clo t = 1 non-m ultiple x ed ale ad15/a15 dependent cd a t a = 0, caddrd a t = 1 8-bit data, t r ansparent m ultiple x ed cd a t a = 1, caddrd a t = 1 16-bit data, ale m ultiple x ed dependent caddrd a t = 0, clo t = 0 non-m ultiple x ed t r ansparent ad0/a0- caddrd a t = 0, clo t = 1 modes ale ad7/a7 dependent caddrd a t = 1 m ultiple x ed modes ale dependent 8-bit data, t r ansparent cd a t a = 0 psen is activ e bhe/ 16-bit data, psen non-m ultiple x ed t r ansparent cd a t a = 1, caddrd a t = 0 mode , bhe is activ e 16-bit data, ale cd a t a = 1, caddrd a t = 1 m ultiple x ed mode , dependent bhe is activ e a19 and caddhl t = 0 a16?19 can t r ansparent pc2?c0 become logic inputs a16?19 can caddhl t = 1 become ale m ultiple x ed dependent address lines t able 8. signal latch status in all operating modes psd3xx family 2-22
figur e 8. page register (psd3x2/3x3/ 3x4r) q clr ck d dff q clr ck d dff q clr ck d dff q clr ck d dff p3 p2 p1 p0 to pad inputs internal wr page select internal rd internal reset ad3 ad2 ad1 ad0 data bus psd3xx family 2-23 memor y paging (psd3x2/3x3/ 3x4r) the page register consists of f our flip-flops , which can be read from, or wr itten to , through the i/o address space (csiopor t). the page register is connected to the d3?0 lines . the p age register address is csiopor t + 18h. the page register outputs are p3?0, which are f ed into the p ad . this enab les the host microcontroller to enlarge its address space b y a f actor of 16 (there can be a maxim um of 16 pages). see figure 8.
psd3xx family 2-24 contr ol signals the psd3xx control signals are wr/v pp or r/w , rd/e or rd/e/ds , ale or as , bhe/psen or psen, reset , and a19/csi. each of these signals can be configured to meet the output control signal requirements of v ar ious microcontrollers . w r / v pp or r / w in oper ational mode , this signal can be configured as wr or r/w . as wr, all wr ite oper ations are activ ated b y an activ e lo w signal on this pin. as r/w , the pin oper ates with the e strobe of the rd/e/ds or rd/e pin. when r/w is high, an activ e high signal on the rd/e/ds or rd/e pin perf or ms a read oper ation. when r/w is lo w , an activ e high signal on the rd/e/ds or rd/e pin perf or ms a wr ite oper ation. r d / e / ds ( or rd/e on psd3x1) in oper ational mode , this signal can be configured as rd , e, or ds . as rd , all read oper ations are activ ated b y an activ e lo w signal on this pin. as e, the pin oper ates with the r/w signal of the wr/v pp or r/w pin. when r/w is high, an activ e high signal on the rd/e/ds pin perf or ms a read oper ation. when r/w is lo w , an activ e high signal on the rd/e/ds pin perf or ms a wr ite oper ation. as ds , the pin functions with the r/w signal as an activ e lo w data strobe signal. as ds , the r/w defines the mode of oper ation (read or wr ite). ale or as ale polar ity is prog r ammab le . when prog r ammed to be activ e high, a high on the pin causes the input address latches , p or t a address latches , p or t c , and a19 address latches to be tr ansparent. the f alling edge of ale loc ks the inf or mation into the latches . when ale is prog r ammed to be activ e lo w , a lo w on the pin causes the input address latches , p or t a address latches , p or t c , and a19 address latches to be tr ansparent. the r ising edge of ale loc ks the appropr iate inf or mation into the latches . bh e / psen this pin s function depends on the psd3xx data b us width. if it is 8 bits , the pin is psen; if it is 16 bits , the pin is bhe. in 8-bit mode , the psen function enab les the user to w or k with tw o address spaces: prog r am memor y and data memor y (if comb/sep = 1). in this mode , an activ e lo w signal on the psen pin causes the epr om to be read if selected. the sram and i/o por ts read oper ation are done b y rd lo w (crr wr = 0), or b y e high and r/w high (crr wr = 1, ceds = 0) or b y ds lo w and r/w high (crr wr, ceds = 1). whene v er a member of the 8031 f amily (or an y other similar microcontroller) is used, the psen pin m ust be connected to the psen pin of the microcontroller . if comb/sep = 0, the address spaces of the prog r am and the data are combined. in this configur ation (e xcept f or the 8031-type case mentioned abo v e), the psen pin m ust be tied high to v cc , and the epr om, sram, and i/o por ts are read b y rd lo w (crr wr = 0), or b y e high and r/w high (crr wr = 1, ceds = 0) or b y ds lo w and r/w high (crr wr, ceds = 1). see figures 9 and 10. in bhe mode , this pin enab les accessing of the upper-half b yte of the data b us . a lo w on this pin enab les a wr ite or read oper ation to be perf or med on the upper half of the data b us (see t ab le 9).
psd3xx family 2-25 figur e 9. combined addr ess space internal oe oe oe cs cs cs rd address psen i/o ports pad sram * eprom bhe a 0 operation 0 0 whole w ord 0 1 upper byte f rom/t o odd address 1 0 lo w er byte f rom/t o ev en address 1 1 none t able 9. high/low byte selection t r uth t able (in 16-bit configuration only) internal oe oe oe cs cs cs rd address psen i/o ports pad sram * eprom figur e 10. 8031-t ype separate code and data addr ess spaces * not a v ailab le on psd3xxr v ersions . * not a v ailab le on psd3xxr v ersions .
psd3xx family 2-26 component signals contents cs0?s10 all = 1 (note 23) p ad csadin, csadout1, csadout2, csiopor t , all = 0 (note 23) rs0, es0 ?es7 data register a n/a 0 direction register a n/a 0 data register b n/a 0 direction register b n/a 0 no te: 23. all p ad outputs are in a non-activ e state . t able 11. inter nal states during and after reset cycle signal configuration mode condition ad0/a0?d7/a7 all input a8?15 all input p a0? a7) i/o input (p or t a) t r ac king ad0/a0?d7 input address outputs a0?7 lo w pb0?b7 i/o input (p or t b) cs7?s0 cmos outputs high cs7?s0 open dr ain outputs t r i-stated pc0?c2 address inputs a16?18 input (p or t c) cs8?s10 cmos outputs high t able 10. signal states during reset active (reset) reset this is an asynchronous input pin that clears and initializ es the psd3xx. reset polar ity is prog r ammab le (activ e lo w or activ e high). whene v er the psd3xx reset input is dr iv en activ e f or at least 100 ns , the chip is reset. the psd3xx m ust be reset at po w er up bef ore it can be used. t ab les 10 and 11 indicate the state of the par t dur ing and after reset. f or the psd3xxl, reset is an asynchronous lo w signal only . whene v er the reset input is dr iv en lo w f or at least 500 ns , the chip is reset. after reset becomes high, the chip will be oper ational only after an additional 500 ns . see figure 11. note that dur ing boot-up , the par t is not automatically reset inter nally and does require an e xter nal reset. t ab les 10 and 11 indicate the state of the par t dur ing and after reset. a19/csi when configured as csi, a high on this pin deselects , and po w ers do wn, the chip . a lo w on this pin puts the chip in nor mal oper ational mode . f or psd3xx states dur ing the po w er-do wn mode , see t ab les 12 and 13, and figure 12. in a19 mode , the pin is an additional input to the p ad . it can be used as an address line (cadlog3 = 1) or as a gener al-pur pose logic input (cadlog3 = 0). a19 can be configured as ale dependent or as tr ansparent input (see t ab le 8). in this mode , the chip is alw a ys enab led. contr ol signals (cont.)
psd3xx family 2-27 reset low v ih reset high psd3xx is operational 500 ns 500 ns v il figur e 11. the reset cycle (reset) (psd3xxl only) t able 12a. signal states during power -down mode (psd30x) signal configuration mode condition ad0/a0?d15/a15 all input i/o unchanged p a0? a7 t r ac king ad0/a0?d7/a7 input address outputs a0?7 all 1 s i/o unchanged pb0?b7 cs0?s7 cmos outputs all 1 s cs0?s7 open dr ain outputs t r i-stated pc0?c2 address inputs a18?16 input cs8?s10 cmos outputs all 1 s signal configuration mode condition ad0/a0?d7/a7 all input a8?15 all input i/o unchanged p a0? a7 t r ac king ad0/a0?d7/a7 input address outputs a0?7 all 1 s i/o unchanged pb0?b7 cs0?s7 cmos outputs all 1 s cs0?s7 open dr ain outputs t r i-stated pc0?c2 address inputs a18?16 input cs8?s10 cmos outputs all 1 s t able 12b. signal states during power -down mode (psd31x)
psd3xx family 2-28 t able 13. inter nal states during power -down component signals contents cs0?s10 all 1 s (deselected) p ad csadin, csadout1, csadout2, csiopor t , all 0 s (deselected) rs0, es0?s7 data register a n/a direction register a n/a all data register b n/a unchanged direction register b n/a figur e 12. a1 9 /csi cell str uctur e cadlog3 conf. bit address latch csi (power-up signal) a19 to pad caddhlt configuration bit: latch or transparent control (note 24) ale cr19/csi conf. bit a19/csi to pad, eprom, sram, ports, latches, etc. address indicator to eprom no tes: 24. the caddhl t configur ation bit deter mines if a19?16 are tr ansparent via the latch, or if the y m ust be latched b y the tr ailing edge of the ale strobe . 25. in the psd3x1, the ca td configur ation bit perf or ms this function f or all the a16?19 lines .
psd3xx family 2-29 system applications in figure 13, the psd3xx is configured to interf ace with intel s 80c31, which is a 16-bit address/8-bit data b us microcontroller . its data b us is m ultiple x ed with the lo w-order address b yte . the 80c31 uses signals rd to read from data memor y and psen to read from code memor y . it uses wr to wr ite into the data memor y . it also uses activ e high reset and ale signals . the rest of the configur ation bits as w ell as the unconnected signals (not sho wn) are application specific and, thus , user dependent. in figure 14, the psd3xx is configured to interf ace with motorola s 68hc11, which is a 16-bit address/8-bit data b us microcontroller . its data b us is m ultiple x ed with the lo w-order address b yte . the 68hc11 uses e and r/w signals to der iv e the read and wr ite strobes . it uses the ter m as (address strobe) f or the address latch pulse . reset is an activ e lo w signal. the rest of the configur ation bits as w ell as the unconnected signals (not sho wn) are specific and, thus , user dependent. figur e 13. psd3xx inter face w ith intel s 80c31 microcontroller 31 19 18 9 12 13 14 15 1 2 3 4 5 6 7 8 23 24 25 26 27 28 29 30 31 32 33 35 36 37 38 39 22 2 1 13 3 p0.0 p0.1 p0.2 p0.3 p0.4 p0.5 p0.6 p0.7 p2.0 p2.1 p2.2 p2.3 p2.4 p2.5 p2.6 p2.7 rd wr psen ale txd rxd pa0 pa1 pa2 pa3 pa4 pa5 pa6 pa7 pb0 pb1 pb2 pb3 pb4 pb5 pb6 pb7 pc0 pc1 pc2 a19/csi 39 38 37 36 35 34 33 32 21 22 23 24 25 26 27 28 17 16 29 30 11 10 21 20 19 18 17 16 15 14 11 10 9 8 7 6 5 4 40 41 42 43 ea/vp x1 x2 reset int0 int1 t0 t1 p1.0 p1.1 p1.2 p1.3 p1.4 p1.5 p1.6 p1.7 ad0/a0 ad1/a1 ad2/a2 ad3/a3 ad4/a4 ad5/a5 ad6/a6 ad7/a7 ad8/a8 ad9/a9 ad10/a10 ad11/a11 ad12/a12 ad13/a13 ad14/a14 ad15/a15 rd wr/v pp bhe/psen ale reset gnd psd3xx 80c31 34 12 v cc 44 0.1? the configur ation bits f or figure 13 are: cale 0 cd a t a 0 caddrd a t 1 creset 1 comb/sep 0 or 1 (both v alid) crr wr 0 ceds 0 all other configur ation bits ma y v ar y according to the application requirements . no te: reset to the psd3xx m ust be the output of a reset chip or b uff er . if reset to the 80c31 is the output of an rc circuit, a separ ate b uff ered rc reset to the psd3xx (shor ter than the 80c31 rc reset) m ust be pro vided to a v oid a r ace condition.
psd3xx family 2-30 the configur ation bits f or figure 14 are: cale 0 cd a t a 0 caddrd a t 1 creset 0 figur e 14. psd3xx inter face w ith motor ola s 68hc11 microcontroller 20 21 22 23 24 25 43 45 47 49 44 46 48 50 34 33 32 31 30 29 28 27 52 51 23 24 25 26 27 28 29 30 31 32 33 35 36 37 38 39 22 2 13 3 1 pc0 pc1 pc2 pc3 pc4 pc5 pc6 pc7 pb0 pb1 pb2 pb3 pb4 pb5 pb6 pb7 e r/w as reset xirq irq modb moda pa0 pa1 pa2 pa3 pa4 pa5 pa6 pa7 pb0 pb1 pb2 pb3 pb4 pb5 pb6 pb7 pc0 pc1 pc2 a19/csi 9 10 11 12 13 14 15 16 42 41 40 39 38 37 36 35 5 6 4 17 18 19 2 3 21 20 19 18 17 16 15 14 11 10 9 8 7 6 5 4 40 41 42 43 pd0 pd1 pd2 pd3 pd4 pd5 pe0 pe1 pe2 pe3 pd4 pe5 pe6 pe7 pa0 pa1 pa2 pa3 pa4 pa5 pa6 pa7 vrh vrl ad0/a0 ad1/a1 ad2/a2 ad3/a3 ad4/a4 ad5/a5 ad6/a6 ad7/a7 ad8/a8 ad9/a9 ad10/a10 ad11/a11 ad12/a12 ad13/a13 ad14/a14 ad15/a15 e r/w/v pp as reset bhe/psen gnd psd3xx 34 12 v cc v cc 68hc11 xtal extal 44 0.1? system applications (cont.) in figure 15, the psd3xx is configured to w or k directly with intel s 80c196kb microcontroller , which is a 16-bit address/16-bit data b us processor . address and data lines m ultiple x ed. in the e xample sho wn, all configur ation bits are set. the psd3xx is configured to use pc0, pc1, pc2, and csi/a19 as a16, a17, a18, and a19 inputs , respectiv ely . these signals are independent of the ale pulse (latch-tr ansparent). the y are used as f our gener al-pur pose logic inputs that tak e par t in the p ad equations implementation. p or t a is configured to w or k in the special tr ac k mode , in which (f or cer tain conditions) p a0? a7 tr ac ks lines ad0/a0?d7/a7. p or t b is configured to gener ate cs0?s7. in this e xample , pb2 ser v es as a w ait signal that slo ws do wn the 80c196kb dur ing the access of e xter nal per ipher als . these 8-bit wide per ipher als are connected to the shared b us of p or t a. the w ait signal also dr iv es the b us width input of the microcontroller , so that e v er y e xter nal per ipher al cycle becomes an 8-bit data b us cycle . pb3 and pb4 are open-dr ain output signals; thus , the y are pulled up e xter nally . comb/sep 0 crr wr 1 ceds 0 all other configur ation bits ma y v ar y according to the application requirements .
psd3xx family 2-31 figur e 15. psd3xx inter face w ith intel s 80c196kb. the configur ation bits f or figure 15 are: cale 0 cd a t a 1 caddrd a t 1 cp af1 don? care cp af2 1 ca19/csi 1 crr wr 0 comb/sep 0 caddhl t 0 creset 0 67 68 36 nmi rxd txd + 5v rst 66 xtal1 ad [ 0 ..15 ] ad [ 0 ..15 ] xtal2 3 43 64 14 16 nmi ready buswidth cde reset 6 5 7 4 11 10 8 9 p0.0 p0.1 p0.2 p0.3 p0.4 p0.5 p0.6 p0.7 18 17 15 44 42 39 33 38 p2.0/txd p2.1/rxd p2.2/exint p2.3/t2clk p2.4/t2rst p2.5/pwm p2.6/ t2 up/dn p2.7/ t2 captr ad0/a0 ad1/a1 ad2/a2 ad3/a3 ad4/a4 ad5/a5 ad6/a6 ad7/a7 ad8/a8 ad9/a9 ad10/a10 ad11/a11 ad12/a12 ad13/a13 ad14/a14 ad15/a15 21 20 19 18 17 16 15 14 11 10 9 8 7 6 5 4 pa0 pa1 pa2 pa3 pa4 pa5 pa6 pa7 pb0 pb1 pb2 pb3 pb4 pb5 pb6 pb7 ad0/a0 ad1/a1 ad2/a2 ad3/a3 ad4/a4 ad5/a5 ad6/a6 ad7/a7 ad8/a8 ad9/a9 ad10/a10 ad11/a11 ad12/a12 ad13/a13 ad14/a14 ad15/a15 ad0/a0 ad1/a1 ad2/a2 ad3/a3 ad4/a4 ad5/a5 ad6/a6 ad7/a7 ad8/a8 ad9/a9 ad10/a10 ad11/a11 ad12/a12 ad13/a13 ad14/a14 ad15/a15 23 24 25 26 27 28 29 30 31 32 33 35 36 37 38 39 40 41 42 43 1 2 22 13 3 pc0 pc1 pc2 a 19/csi bhe /psen wr / v pp rd ale reset 24 25 26 27 hsi.0 hsi.1 hsi.2/hso.4 hsi.3/hso.5 13 37 12 2 vref vpp angnd ea 19 20 21 22 23 30 31 32 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 65 41 40 61 62 63 28 29 34 35 p1.0 p1.1 p1.2 p1.3 p1.4 p1.5 p1.6 p1.7 p3.0/ad0 p3.1/ad1 p3.2/ad2 p3.3/ad3 p3.4/ad4 p3.5/ad5 p3.6/ad6 p3.7/ad7 p4.0/ad8 p4.1/ad9 p4.2/ad10 p4.3/ad11 p4.4/ad12 p4.5/ad13 p4.6/ad14 p4.7/ad15 clkout bhe / wrh wr / wrl rd ale /adv inst hso.0 hso.1 hso.2 hso.3 0.1? 0.1? four general purpose inputs gnd gnd 12 34 +5v +5v +5v 4.7k w 4.7k w 0.1? ale wait shared bus port 1 i/o pins 44 v cc v cc v ss v ss address/data multiplexed bus 80c196kb psd3xx csecurity don? care cpcf2, cpcf1, cpcf0 0, 0, 0 cp a cod7?p a cod0 00h cpbf7?pbf0 00h cpbcod7?pbcod0 18h ceds 0 cadlog3?adlog0 0h
psd3xx family 2-32 secur ity mode in the psd3xx loc ks the contents of the p ad a , p ad b and all the configur ation bits . the epr om, sram, and i/o contents can be accessed only through the p ad . the secur ity mode can be set b y the psd de v elopment or prog r amming softw are . in windo w pac kages , the mode is er asab le through uv full par t er asure . in the secur ity mode , the psd3xx contents cannot be copied on a prog r ammer . symbol parameter condition min max unit t stg stor age t emper ature cerdip ?65 + 150 c plastic ?65 + 125 c v oltage on an y pin with respect to gnd ?0.6 + 7 v v pp prog r amming supply v oltage with respect to gnd ?0.6 + 14 v v cc supply v oltage with respect to gnd ?0.6 + 7 v esd protection > 2000 v range t emperatur e v c c v c c t olerance commercial 0 c to +70 c + 5 v 10% industr ial 40 c to +85 c + 5 v 10% militar y 55 c to +125 c + 5 v 10% symbol parameter conditions min t yp max unit v cc supply v oltage all speeds 4.5 5 5.5 v v cc supply v oltage psd3xxl v ersions only , all speeds 3.0 3.3 5.5 v the epr om po w er consumption in the psd is controlled b y bit 3 in the pmmr0 ?epr om cmiser . upon reset the cmiser bit is off . this will cause the epr om to be on at all times as long as csi is enab led (lo w). the reason this mode is pro vided is to reduce the access time of the epr om b y 10 ns relativ e to the lo w po w er condition when cmiser is on. if csi is disab led (high) the epr om will be deselected and will enter standb y mode (off) o v err iding the state of the cmiser . if cmiser is set (on) then the epr om will enter the standb y mode when not selected. this condition can tak e place when csi is high or when csi is lo w and the epr om is not accessed. f or e xample , if the mcu is accessing the sram, the epr om will be deselected and will be in lo w po w er mode . an additional adv antage of the cmiser is achie v ed when the psd is configured in the b y 8 mode (8 bit data b us). in this case an additional po w er sa vings is achie v ed in the epr om (and also in the sram) b y tur ning off 1/2 of the arr a y e v en when the epr om is accessed (the arr a y is divided inter nally into odd and e v en arr a ys). the po w er consumption f or the diff erent epr om modes is giv en in the dc char acter istics tab le under i cc (dc) epr om adder . security mode eprom absolute maximum rating s 26 operating range recommended operating conditions no te: 26. stresses abo v e those listed under absolute maxim um ratings ma y cause per manent damage to the de vice . this is a stress r ating only and functional oper ation of the de vice at these or an y other conditions abo v e those indicated in the oper ational sections of this specification is not implied. exposure to absolute maxim um rating conditions f or e xtended per iods of time ma y aff ect de vice reliability .
cmiser = 1 subtract: symbol parameter conditions min t yp max min t yp max unit v i h high-le v el input v oltage v cc = 4.5 v to 5.5 v 2 v cc + . 1 v v i l lo w-le v el input v oltage v cc = 4.5 v to 5.5 v 0.5 0.8 v i oh = 20 a, 4.4 4.49 v v cc = 4.5 v v oh output high v oltage i oh = 2 ma, 2.4 3.9 v v cc = 4.5 v i ol = 20 a v cc = 4.5 v 0.01 0.1 v v ol output lo w v oltage i ol = 8 ma v cc = 4.5 v 0.15 0.45 v i sb1 v cc standb y current comm'l 50 100 a (cmos) (notes 27 and 29) ind/mil 75 150 a activ e current (cmos) comm'l (note 31) 16 35 7 10 ma (no inter nal memor y comm'l (note 32) 28 50 7 10 ma i cc1 bloc k selected) ind/mil (note 31) 16 45 7 10 ma (notes 27, 28a and 30) ind/mil (note 32) 28 60 7 10 ma activ e current (cmos) comm? (note 31) 16 35 0/5 * 0/7 * ma i cc2 (epr om bloc k selected) comm'l (note 32) 28 50 0/5 * 0/7 * ma (notes 27, 28a and 30) ind/mil (note 31) 16 45 0/5 * 0/7 * ma ind/mil (note 32) 28 60 0/5 * 0/7 * ma activ e current (cmos) comm? (note 31) 47 80 7 10 ma i cc3 (sram bloc k selected) comm'l (note 32) 59 95 7 10 ma (notes 27, 28a and 30) ind/mil (note 31) 47 100 7 10 ma ind/mil (note 32) 59 115 7 10 ma i li input leakage current v in = 5.5 v or gnd ? 0.1 1 a i lo output leakage current v out = 5.5 v or gnd ?0 5 10 a dc characteristics ? psd3xx v ersions (5v 10%) psd3xx family 2-33 no tes: 27. cmos inputs: gnd 0.3 v or v cc 0.3v . 28. ttl inputs: v il 0.8 v , v ih 3 2.0 v . 28a. i out = 0 ma. 29. csi/a19 is high and the par t is in a po w er-do wn configur ation mode . 30. add 3.0 ma/mhz f or a c po w er component (po w er = a c + dc). 31. t en (10) p ad product ter ms activ e . (add 380 a per product ter m, typical, or 480 a per product ter m maxim um.) 32. f or ty-one (41) p ad product ter ms activ e . * the z ero v alue is f or 16-bit configur ations . the other v alues are f or 8-bit configur ations .
psd3xx family 2-34 cmiser = 1 subtract: symbol parameter conditions min t yp max min t yp max unit v i h high-le v el input v oltage v cc = 3.0 v to 5.5 v 0.7 v cc v c c + 0.5 v v i l lo w-le v el input v oltage v cc = 3.0 v to 5.5 v 0.5 0.3 v c c v i oh = 20 a, 2.9 2.99 v v cc = 3.0 v v oh output high v oltage i oh = 1 ma, v cc = 3.0 v 2.4 2.6 v i ol = 20 a, v cc = 3.0 v 0.01 0.1 v v ol output lo w v oltage i ol = 4 ma, v cc = 3.0 v 0.15 0.4 v i sb1 v cc standb y current v cc = 3.3 v (cmos) (notes 33 and 34) 1 5 a activ e current (cmos) v cc = 3.3 v 5 11 3.0 4 ma (no inter nal memor y (note 36) i cc1 bloc k selected) v cc = 3.3 v 9 17 3.0 4 ma (notes 33, 33a and 35) (note 37) activ e current (cmos) v cc = 3.3 v 5 11 0/2 * 0/3 * ma (epr om bloc k selected) (notes 36 and 38) i cc2 (notes 33, 33a and 35) v cc = 3.3 v 9 17 0/2 * 0/3 * ma (notes 37 and 38) activ e current (cmos) v cc = 3.3 v 16 29 3 4 ma (sram bloc k selected) (notes 36 and 38) i cc3 (notes 33, 33a and 35) v cc = 3.3 v 21 35 3 4 ma (notes 37 and 38) i li input leakage current v in = v cc or gnd ? 0.1 1 a i lo output leakage current v out = v cc or gnd ?0 5 10 a dc characteristics ? psd3xxl low-power v ersions (3.3v 10%) no tes: 33. cmos inputs: gnd 0.3 v or v cc 0.3v . 33a. i out = 0 ma. 34. csi/a19 is high and the par t is in a po w er-do wn configur ation mode . 35. a c po w er component (po w er = a c + dc). ? f or 3.3 v oper ation, add 2.0 ma/mhz. ? f or 5.0 v oper ation, add 3.0 ma/mhz. 36. t en (10) p ad product ter ms activ e . (add 190 a per product ter m, typical, or 240 a per product ter m maxim um.) 37. f or ty (40) p ad product ter ms activ e . 38. in 8-bit mode , an additional 3 ma max can be sa v ed under cmiser . *the z ero v alue is f or 16-bit configur ations . the other v alues are f or 8-bit configur ations .
psd3xx family 2-35 the nor maliz ed supply current vs . supply v oltage g r aph sho wn abo v e , pro vides a m ultiplier f or an y i sb or i cc v alue in the d .c . char acter istics tab le . as noted, it is nor maliz ed f or a supply v oltage of 3.3 v olts (psd3xxl v ersions). t o use , calculate the supply current at 3.3 v olts f or y our oper ation configur ation using the d .c . char acter istics tab le . then m ultiply that v alue b y the supply current multiplier f or the supply v oltage actually being used. 3.0 3.3 3.5 4.0 4.5 5.0 5.5 supply voltage (v) normalized supply current multiplier 3.5 3.0 2.5 2.0 1.5 1.0 0.5 dc 3.0 3.5 4.0 4.5 5.0 5.5 supply voltage (v) normalized access time multiplier (t6) 1.0 0.9 0.8 0.7 0.6 0.5 figure 16a. normalized access time multiplier vs. supply voltage (psd3xxl low-power versions) figur e 16. nor malized supply cur r ent vs. supply v oltage (psd3xxl low-power v ersions)
psd3xx family 2-36 -70 -90 -12 -15 -20 cmiser symbol parameter on = unit min max min max min max min max min max add t1 ale or as pulse width 18 20 30 40 50 0 ns t2 address set-up time 5 5 9 12 15 0 ns t3 address hold time 7 8 9 10 15 0 ns t4 leading edge of read to data activ e 0 0 0 0 0 0 ns t5 ale v alid to data v alid 80 100 140 170 200 10 ns t6 address v alid to data v alid 70 90 120 150 210 10 ns t7 csi activ e to data v alid 80 100 150 160 200 10 ns t8 leading edge of read to data v alid 20 32 36 45 50 0 ns leading edge of read to data v alid in t8a 8031-based architecture 32 32 38 55 60 0 ns oper ating with psen and rd in separ ate mode t9 read data hold time 0 0 0 0 0 0 ns t r ailing edge of read to data high-z 20 35 35 40 45 0 ns t10 (psd3x1) t r ailing edge of read to data high-z 20 30 35 40 45 0 ns (psd3x2/3x3/3x4r) t r ailing edge of ale t11 or as to leading edge 0 0 0 0 0 0 ns of wr ite t12 rd , e, psen, or ds pulse width 35 40 45 60 75 0 ns t12a wr pulse width 18 20 25 35 45 0 ns t r ailing edge of wr ite t13 or read to leading edge 5 5 5 5 5 0 ns of ale or as t14 address v alid to t r ailing edge of wr ite 70 90 120 150 200 0 ns csi activ e to t r ailing t15 edge of wr ite 80 100 130 160 200 0 ns t16 wr ite data set-up time 18 20 25 30 40 0 ns ac characteristics ? psd3xx v ersions (5v 10%)
psd3xx family 2-37 -70 -90 -12 -15 -20 cmiser symbol parameter on = unit min max min max min max min max min max add t17 wr ite data hold time 5 5 5 10 15 0 ns t18 p or t to data out v alid propagation dela y 25 28 30 35 45 0 ns t19 p or t input hold time 0 0 0 0 0 0 ns t20 t r ailing edge of wr ite to p or t output v alid 30 35 40 50 60 0 ns t21 adi or control to csoi v alid 6 20 6 25 6 30 6 35 5 45 10 ns t22 adi or control to csoi in v alid 5 20 5 25 5 30 4 35 4 45 10 ns t r ac k mode address propagation dela y: 22 22 22 22 28 0 ns t23 csadout1 already t r ue latched address outputs , p or t a 22 22 22 22 28 0 ns t r ac k mode address propagation dela y: t23a csadout1 becomes 33 33 33 40 50 10 ns t r ue dur ing ale or as t r ac k mode t r ailing edge t24 of ale or as to address 30 32 32 35 40 0 ns high-z t r ac k mode read t25 propagation dela y 27 29 29 29 35 0 ns t26 t r ac k mode read hold time 5 29 11 29 11 29 11 29 11 35 0 ns t r ac k mode wr ite cycle , t27 data propagation dela y 18 20 20 20 30 0 ns t r ac k mode wr ite t28 cycle , wr ite to data 6 30 8 30 8 30 9 40 9 55 0 ns propagation dela y hold time of p or t a t29 v alid dur ing wr ite 2 2 2 2 2 0 ns csoi t r ailing edge csi activ e to csoi activ e (psd3x1) 8 37 9 40 9 45 9 45 8 60 0 ns t30 csi activ e to csoi activ e (psd3x2/3x3/3x4r) 8 37 9 40 9 45 9 50 8 60 0 ns csi inactiv e to csoi t31 inactiv e 8 37 9 40 9 45 9 45 8 60 0 ns t32 direct p ad input as hold time 0 0 0 0 0 0 ns ac characteristics ? psd3xx v ersions (5v 10%) (cont.)
psd3xx family 2-38 no tes: 39. adi = an y address line . 40. csoi = an y of the chip-select output signals coming through p or t b (cs0?s7) or through p or t c (cs8?s10). 41. direct p ad input = an y of the f ollo wing direct p ad input lines: csi/a19 as tr ansparent a19, rd/e/ds , wr or r/w , tr ansparent pc0?c2, ale (or as). 42. control signals rd/e/ds or wr or r/w . 40 35 30 25 20 15 10 5 0 0.00 0.10 0.20 0.30 0.40 0.50 0.60 0.70 0.80 v ol (v) i ol (ma) temp. = 125? temp. = 25? -70 -90 -12 -15 -20 cmiser symbol parameter on = unit min max min max min max min max min max add r/w activ e to e high (psd3x1) 18 20 20 30 40 0 ns t33 r/w activ e to e or ds star t (psd3x2/3x3/3x4r) 18 20 20 30 40 0 ns e end to r/w (psd3x1) 18 20 20 30 40 0 ns t34 e or ds end to r/w 18 20 20 30 40 0 ns (psd3x2/3x3/3x4r) t35 as inactiv e to e high 0 0 0 0 0 0 ns t36 address to leading edge of wr ite 18 20 20 25 30 0 ns ac characteristics ? psd3xx v ersions (5v 10%) (cont.) figur e 17. psd3xx i ol vs. v ol
-15 -20 -25 -30 cmiser = 1 symbol parameter min max min max min max min max add: unit t1 ale or as pulse width 40 50 75 80 ns t2 address set-up time 12 15 30 35 ns t3 address hold time 10 15 20 30 0 ns leading edge of read t4 to data activ e 0 0 0 0 0 ns t5 ale v alid to data v alid 160 200 250 300 20 ns t6 address v alid to data v alid 150 200 250 300 20 ns t7 csi activ e to data v alid 160 210 275 325 20 ns t8 leading edge of read to data v alid 40 45 90 95 0 ns t8a leading edge of read to data v alid 60 65 90 95 0 ns t9 read data hold time 0 0 0 0 0 ns t10 t r ailing edge of read to data high-z 40 45 55 60 0 ns t r ailing edge of ale or as t11 to leading edge of wr ite 0 0 40 45 ns t12 rd , e, psen, ds pulse width 60 75 100 110 0 ns t12a wr pulse width 35 45 90 95 0 ns t r ailing edge of wr ite or read t13 to leading edge of ale or as 5 5 5 5 0 ns address v alid to t r ailing t14 edge of wr ite 150 200 250 300 0 ns csi activ e to t r ailing edge t15 of wr ite 160 200 275 325 0 ns t16 wr ite data set-up time 30 40 60 65 0 ns t17 wr ite data hold time 10 12 25 30 0 ns t18 p or t to data out v alid propagation dela y 40 45 70 75 0 ns t19 p or t input hold time 0 0 0 0 0 ns t20 t r ailing edge of wr ite to p or t output v alid 50 60 100 110 0 ns t21 adi or control to csoi v alid 6 45 5 50 6 80 5 85 0 ns t22 adi or control to csoi in v alid 4 45 4 50 4 80 4 85 0 ns ac characteristic s ? psd3xxl low-power v ersions (3.3v 10%, note 43) psd3xx family 2-39 no te: 43. these a c char acter istics are f or v cc = 3.0 ?3.6v .
psd3xx family 2-40 -15 -20 -25 -30 cmiser = 1 symbol parameter min max min max min max min max add: unit t r ac k mode address propagation t23 dela y: csadout1 already t r ue 50 60 70 75 0 ns latched address outputs , p or t a 50 60 70 75 0 t r ac k mode address t23a propagation dela y: 70 80 100 110 0 ns csadout1 becomes t r ue dur ing ale or as t r ac k mode t r ailing edge of ale t24 or as to address high-z 45 55 60 65 0 ns t25 t r ac k mode read propagation dela y 40 50 70 75 0 ns t26 t r ac k mode read hold time 10 70 10 70 10 70 10 75 ns t r ac k mode wr ite cycle , t27 data propagation dela y 40 50 60 65 0 ns t28 t r ac k mode wr ite cycle , wr ite to data propagation dela y 8 65 8 75 9 80 9 85 0 ns t29 hold time of p or t a v alid dur ing wr ite csoi t r ailing edge 2 3 4 4 0 ns t30 csi activ e to csoi activ e 9 55 9 70 9 110 8 120 0 ns t31 csi inactiv e to csoi inactiv e 9 55 9 70 9 110 8 120 0 ns t32 direct p ad input as hold time 0 0 0 0 0 ns t33 r/w activ e to e or ds star t 30 40 60 65 0 ns t34 e or ds end to r/w 30 40 60 65 0 ns t35 as inactiv e to e high 0 0 40 45 0 ns t36 address to leading edge of wr ite 25 30 50 60 0 ns no tes: 44. adi = an y address line . 45. csoi = an y of the chip-select output signals coming through p or t b (cs0?s7) or through p or t c (cs8?s10). 46. direct p ad input = an y of the f ollo wing direct p ad input lines: csi/a19 as tr ansparent a19, rd/e/ds , wr or r/w , tr ansparent pc0?c2, ale (or as). 47. control signals rd/e/ds or wr or r/w . ac characteristic s ? psd3xxl low-power v ersions (3.3v 10%, note 43 ) (cont.)
psd3xx family 2-41 figur e 18. t iming of 8-bit multiplexed addr es s /data bus, crr wr = 0 (psd3x1) 18 data valid csi/a19 as csi data in 8 12 1 7 15 32 32 14 14 6 6 10 9 address a address b 2 3 4 13 32 5 2 16 17 12a 19 13 20 23 23 address a address b input input output output read cycle write cycle stable input stable input direct (48) pad input multiplexed (49) inputs a0/ad0- a7/ad7 active low ale active high ale rd/e as rd bhe/psen as psen wr/v pp or rw as wr any of pa0-pa7 as i/o pin any of pa0-pa7 pins as address outputs any of pb0-pb7 as i/o pin 1 3 11 36 see ref erenced notes on page 2-61.
psd3xx family 2-42 figur e 19. t iming of 8-bit multiplexed addr es s /data bus, crr wr = 0 (psd3x2/3x3/3x4r) 18 data valid csi/a19 as csi data in 8 12 1 7 15 32 32 14 14 6 6 10 9 address a address b 2 3 4 13 32 5 2 16 17 12a 19 13 20 23 23 address a address b input input output output read cycle write cycle stable input stable input direct (48) pad input multiplexed (49) inputs a0/ad0- a7/ad7 active low ale active high ale rd/e/ds as rd bhe/psen as psen wr/v pp or rw as wr any of pa0-pa7 as i/o pin any of pa0-pa7 pins as address outputs any of pb0-pb7 as i/o pin 1 3 11 36 see ref erenced notes on page 2-61.
psd3xx family 2-43 figur e 20. t iming of 8-bit multiplexed addr es s /data bus, crr wr = 1 (psd3x1) 18 33 34 36 19 data valid csi/a19 as csi data in 8 12 5 1 32 7 15 32 32 14 14 6 6 10 9 address a address b 2 3 4 33 13 2 16 17 12 13 20 23 23 address a address b input input output output read cycle write cycle stable input stable input direct (48) pad input multiplexed (49) inputs a0/ad0- a7/ad7 active low as active high as rd/e as e wr/v pp or r/w as r/w any of pa0-pa7 as i/o pin any of pa0-pa7 pins as address outputs any of pb0-pb7 as i/o pin 1 3 34 35 35 see ref erenced notes on page 2-61.
psd3xx family 2-44 figur e 21. t iming of 8-bit multiplexed addr es s /data bus, crr wr = 1 (psd3x2/3x3/3x4r) 18 33 34 36 19 data valid csi/a19 as csi data in 8 12 5 1 32 7 15 32 32 14 14 6 6 10 9 address a address b 2 3 4 33 13 2 16 17 12 13 20 23 23 address a address b input input output output read cycle write cycle stable input stable input direct (48) pad input multiplexed (49) inputs a0/ad0- a7/ad7 active low as active high as rd/e/ds as e wr/v pp or r/w as r/w any of pa0-pa7 as i/o pin any of pa0-pa7 pins as address outputs any of pb0-pb7 as i/o pin 1 3 34 35 rd/e/ds as ds 35 see ref erenced notes on page 2-61.
psd3xx family 2-45 figur e 22. t iming of 16-bit multiplexed addr es s /data bus, crr wr = 0 (psd3x1) 18 36 4 19 data valid csi/a19 as csi 12 5 1 7 15 32 32 14 14 6 6 10 9 address a address b 2 3 8 13 2 16 17 12a 13 20 23 23 address a address b input input output output read cycle write cycle stable input stable input direct (48) pad input multiplexed (49) inputs data in a0/ad0- a15/ad15 active low ale active high ale rd/ e as rd bhe/psen as bhe any of pa0-pa7 as i/o pin any of pa0-pa7 pins as address outputs any of pb0-pb7 as i/o pin 1 3 11 wr/v pp or r/w as wr 32 see ref erenced notes on page 2-61.
psd3xx family 2-46 figur e 23. t iming of 16-bit multiplexed addr es s /data bus, crr wr = 0 (psd3x2/3x3/3x4r) 18 36 4 19 data valid csi/a19 as csi 12 5 1 7 15 32 32 14 14 6 6 10 9 address a address b 2 3 8 13 2 16 17 12a 13 20 23 23 address a address b input input output output read cycle write cycle stable input stable input direct (48) pad input multiplexed (49) inputs data in a0/ad0- a15/ad15 active low ale active high ale rd/ e/ds as rd bhe/psen as bhe any of pa0-pa7 as i/o pin any of pa0-pa7 pins as address outputs any of pb0-pb7 as i/o pin 1 3 11 wr/v pp or r/w as wr 32 see ref erenced notes on page 2-61.
psd3xx family 2-47 figur e 24. t iming of 16-bit multiplexed addr es s /data bus, crr wr = 1 (psd3x1) 18 19 33 data valid csi/a19 as csi 1 32 7 15 32 32 14 14 6 6 10 9 address a address b 2 3 35 13 4 2 16 17 20 23 23 address a address b input input output output read cycle write cycle stable input stable input direct (48) pad input multiplexed (49) inputs data in a0/ad0- a15/ad15 active low as active high as bhe/psen as bhe any of pa0-pa7 as i/o pin any of pa0-pa7 pins as address outputs any of pb0-pb7 as i/o pin 1 3 35 34 34 33 8 12 5 12 13 as e rd/e as e as e wr/v pp or r/w as r/w 36 see ref erenced notes on page 2-61.
psd3xx family 2-48 figur e 25. t iming of 16-bit multiplexed addr es s /data bus, crr wr = 1 (psd3x2/3x3/3x4r) 18 19 33 data valid csi/a19 as csi 1 32 7 15 32 32 14 14 6 6 10 9 address a address b 2 3 35 13 4 2 16 17 20 23 23 address a address b input input output output read cycle write cycle stable input stable input direct (48) pad input multiplexed (49) inputs data in a0/ad0- a15/ad15 active low as active high as bhe/psen as bhe any of pa0-pa7 as i/o pin any of pa0-pa7 pins as address outputs any of pb0-pb7 as i/o pin 1 3 35 34 34 33 8 12 5 12 13 rd/e/ds as e rd/e/ds as e rd/e/ds as e rd/e/ds as e wr/v pp or r/w as r/w rd/e/ds as ds 36 see ref erenced notes on page 2-61.
psd3xx family 2-49 figur e 26. t iming of 8-bit non-multiplexed addr es s /data bus, crr wr = 0 (psd3x1) 18 8 19 data valid csi/a19 as csi 12 5 1 7 15 32 14 14 6 6 10 9 2 3 4 32 13 2 16 17 12a 13 20 input output read cycle write cycle stable input stable input a0/ad0- a15/ad15 as a0-a15 stable input stable input direct (48) pad input pc0-pc2, csi/a19 as multiplexed inputs data in pa0-pa7 active low ale active high ale rd/e as rd any of pb0-pb7 as i/o pin 1 3 11 32 32 wr/v pp or r/w as wr 36 see ref erenced notes on page 2-61.
psd3xx family 2-50 figur e 27. t iming of 8-bit non-multiplexed addr es s /data bus, crr wr = 0 (psd3x2/3x3/3x4r) 18 8 19 data valid csi/a19 as csi 12 5 1 7 15 32 14 14 6 6 10 9 2 3 4 32 13 2 16 17 12a 13 20 input output read cycle write cycle stable input stable input a0/ad0- a15/ad15 as a0-a15 stable input stable input direct (48) pad input multiplexed (49) inputs data in pa0-pa7 active low ale active high ale rd/e/ds as rd any of pb0-pb7 as i/o pin 1 3 11 32 32 wr/v pp or r/w as wr 36 see ref erenced notes on page 2-61.
psd3xx family 2-51 figur e 28. t iming of 8-bit non-multiplexed addr es s /data bus, crr wr = 1 (psd3x1) 8 data valid csi/a19 as csi 1 7 15 32 32 14 14 6 6 10 9 2 3 35 32 32 2 16 17 read cycle write cycle stable input stable input a0/ad0- a15/ad15 as a0-a15 stable input stable input direct (48) pad input pc0-pc2, csi/a19 as multiplexed inputs data in pa0-pa7 active low ale active high ale 1 3 35 18 12 19 33 13 20 input output any of pb0-pb7 as i/o pin 4 34 34 33 12 13 rd/e as e as e as e as e wr/v pp or r/w as r/w 36 see ref erenced notes on page 2-61.
psd3xx family 2-52 figur e 29. t iming of 8-bit non-multiplexed addr es s /data bus, crr wr = 1 (psd3x2/3x3/3x4r) 8 data valid csi/a19 as csi 1 7 15 32 32 14 14 6 6 10 9 2 3 35 32 32 2 16 17 read cycle write cycle stable input stable input a0/ad0- a15/ad15 as a0-a15 stable input stable input direct (48) pad input multiplexed (49) inputs data in pa0-pa7 active low ale active high ale 1 3 35 36 18 19 33 13 20 input output any of pb0-pb7 as i/o pin 4 34 34 33 12 5 12 13 rd/e/ds as e rd/e/ds as e rd/e/ds as e rd/e/ds as e wr/v pp or r/w as r/w rd/e/ds as ds see ref erenced notes on page 2-61.
psd3xx family 2-53 figur e 30. t iming of 16-bit non-multiplexed addr es s /data bus, crr wr = 0 (psd3x1) 8 csi/a19 as csi 1 32 7 15 32 32 14 6 6 4 32 read cycle write cycle stable input stable input a0/ad0- a15/ad15 as a0-a15 stable input stable input direct (48) pad input pc0-pc2, csi/a19 as multiplexed inputs data in active low ale active high ale 1 3 3 2 2 11 13 12 12a 13 rd/e as rd wr/v pp or r/w as wr data valid 14 10 9 9 pa0-pa7 (low byte) data in data valid 17 16 pb0-pb7 (high byte) bhe/psen as bhe 36 see ref erenced notes on page 2-61.
psd3xx family 2-54 figur e 31. t iming of 16-bit non-multiplexed addr es s /data bus, crr wr = 0 (psd3x2/3x3/3x4r) 8 csi/a19 as csi 1 32 7 15 32 32 14 6 6 4 32 read cycle write cycle stable input stable input a0/ad0- a15/ad15 as a0-a15 stable input stable input direct (48) pad input multiplexed (49) inputs data in active low ale active high ale 1 3 3 2 2 11 13 12 5 12a 13 rd/e/ds as rd wr/v pp or r/w as wr data valid 14 10 9 pa0-pa7 (low byte) data in data valid 17 16 pb0-pb7 (high byte) bhe/psen as bhe 36 see ref erenced notes on page 2-61.
psd3xx family 2-55 figur e 32. t iming of 16-bit non-multiplexed addr es s /data bus, crr wr = 1 (psd3x1) csi/a19 as csi 1 32 7 15 32 32 14 6 6 4 35 32 read cycle write cycle stable input stable input a0/ad0- a15/ad15 as a0-a15 stable input stable input direct (48) pad input pc0-pc2, csi/a19 as multiplexed inputs data in active low as active high as 1 3 3 8 2 2 35 33 data valid 14 10 9 pa0-pa7 (low byte) data in data valid 17 16 pb0-pb7 (high byte) bhe/psen as bhe 13 34 34 33 12 13 rd/e as e as e as e as e wr/v pp or r/w as r/w 36 see ref erenced notes on page 2-61.
psd3xx family 2-56 figur e 33. t iming of 16-bit non-multiplexed addr es s /data bus, crr wr = 1 (psd3x2/3x3/3x4r) csi/a19 as csi 1 32 7 15 32 32 14 6 6 4 35 32 read cycle write cycle stable input stable input a0/ad0- a15/ad15 as a0-a15 stable input stable input direct (48) pad input multiplexed (49) inputs data in active low as active high as 1 3 3 8 2 2 35 33 data valid 14 10 9 pa0-pa7 (low byte) data in data valid 17 16 pb0-pb7 (high byte) bhe/psen as bhe 13 34 34 33 12 5 12 13 rd/e/ds as e rd/e/ds as e rd/e/ds as e rd/e/ds as e wr/v pp or r/w as r/w rd/e/ds as ds 36 see ref erenced notes on page 2-61.
psd3xx family 2-57 figur e 34. chip-select output t iming (psd30x) 30 21 31 a19/csi as csi direct pad (48) input multiplexed (49) pad inputs csoi (50,55) ale (multiplexed mode only) or ale (multiplexed mode only) 22 1 2 3 input stable see ref erenced notes on page 2-61.
psd3xx family 2-58 figur e 35. por t a as ad 0 ad7 t iming (t rack mode), crr wr = 0 (psd3x1) 25 32 32 12a 28 24 11 data valid 12 1 32 32 24 26 2 address address 2 3 2 2 4 read cycle write cycle stable input stable input stable input stable input direct pad input (48,51) multiplexed pad inputs (52,54) a0/ad0- a7/ad7 or ale ale rd/e as rd wr/v pp or r/w as wr 1 3 27 pa0-pa7 29 csoi (50,53) data in data out written data 23 adr out 23 adr out see ref erenced notes on page 2-61.
psd3xx family 2-59 figur e 36. por t a as ad 0 ad7 t iming (t rack mode), crr wr = 0 (psd3x2/3x3/3x4r) 25 32 32 12a 28 24 11 data valid 12 1 32 32 24 26 2 address address 2 3 2 2 4 read cycle write cycle stable input stable input stable input stable input direct pad input (48,51) multiplexed pad inputs (52,54) a0/ad0- a7/ad7 or ale ale rd/e/ds as rd wr/v pp or r/w as wr 1 3 27 pa0-pa7 29 csoi (50,53) data in data out written data 23 adr out 23 adr out see ref erenced notes on page 2-61.
psd3xx family 2-60 figur e 37. por t a as ad0?d7 t iming (t rack mode), crr wr = 1 (psd3x1) 33 25 33 32 12 28 24 34 35 data valid 12 1 32 32 32 23 24 26 2 address address 2 3 2 35 read cycle write cycle stable input stable input stable input stable input direct pad input (48,51) multiplexed pad inputs (52,54) a0/ad0- a7/ad7 or as as rd/e as e as e as e as e wr/v pp or r/w as r/w 1 3 34 27 23 pa0-pa7 29 csoi (50,53) adr out data in data out written data adr out see ref erenced notes on page 2-61.
psd3xx family 2-61 figur e 38. por t a as ad0?d7 t iming (t rack mode), crr wr = 1 (psd3x2/3x3/3x4r) 33 25 33 32 12 28 24 34 35 data valid 12 1 32 32 32 23 24 26 2 address address 2 3 2 35 read cycle write cycle stable input stable input stable input stable input direct pad input (48,51) multiplexed pad inputs (52,54) a0/ad0- a7/ad7 or as as rd/e/ds as e rd/e/ds as e rd/e/ds as e rd/e/ds as e wr/v pp or r/w as r/w 1 3 34 27 23 rd/e/ds as ds pa0-pa7 29 csoi (50,53) adr out data in data out written data adr out 48. direct p ad input = an y of the f ollo wing direct p ad input lines: csi/a19 as tr ansparent a19, rd/e/ds , wr or r/w , tr ansparent pc0?c2, ale in non-m ultiple x ed modes . 49. multiple x ed inputs: an y of the f ollo wing inputs that are latched b y the ale (or as): a0/ad0?15/ad15, csi/a19 as ale dependent a19, ale dependent pc0?c2. 50. csoi = an y of the chip-select output signals coming through p or t b (cs0?s7) or through p or t c (cs8?s10). 51. csadout1, which inter nally enab les the address tr ansf er to p or t a, should be der iv ed only from direct p ad input signals , otherwise the address propagation dela y is slo w ed do wn. 52. csadin and csadout2, which inter nally enab le the data-in or data-out tr ansf ers , respectiv ely , can be der iv ed from an y combination of direct p ad inputs and m ultiple x ed p ad inputs . 53. the wr ite oper ation signals are included in the csoi e xpression. 54. multiple x ed p ad inputs: an y of the f ollo wing p ad inputs that are latched b y the ale (or as) in the m ultiple x ed modes: a11/ad11?15/ad15, csi/a19 as ale dependent a19, ale dependent pc0?c2. 55. csoi product ter ms can include an y of the p ad input signals sho wn in figure 3, e xcept f or reset and csi. notes for t iming diagrams
psd3xx family 2-62 symbol parameter conditions t ypica l 57 max unit c in capacitance (f or input pins only) v in = 0 v 4 6 pf c out capacitance (f or input/output pins) v out = 0 v 8 12 pf c vpp capacitance (f or wr/v pp or r/w/v pp ) v pp = 0 v 18 25 pf no tes: 56. this par ameter is only sampled and is not 100% tested. 57. t ypical v alues are f or t a = 25 c and nominal supply v oltages . t able 14. pin capacitanc e 56 figur e 39. ac t esting inpu t / output w avefor m (psd3xx v ersions) figur e 40. ac t esting load cir cuit (psd3xx v ersions) 3.0v 0v test point 1.5v figur e 39a. ac t esting inpu t / output w avefor m (psd3xxl v ersions) figur e 40a. ac t esting load cir cuit (psd3xxl v ersions) 0.9v cc 0v test point 1.5v device under test 2.01 v 195 w c l = 30 pf (including scope and jig capacitance) device under test 2.0 v 400 w c l = 30 pf (including scope and jig capacitance)
psd3xx family 2-63 t o clear all locations of their prog r ammed contents , e xpose the windo w pac kaged de vice to an ultr a-violet light source . a dosage of 30 w second/c m 2 is required (40 w second/c m 2 f or psd3xxl v ersions). this dosage can be obtained with e xposure to a w a v elength of 2537 ? and intensity of 12000 w/c m 2 f or 40 to 45 min utes (50 to 60 min utes f or psd3xxl v ersions). the de vice should be about 1 inch from the source , and all filters should be remo v ed from the uv light source pr ior to er asure . the psd3xx and similar de vices will er ase with light sources ha ving w a v elengths shor ter than 4000 ?. although the er asure times will be m uch longer than with uv sources at 2537 ?, e xposure to fluorescent light and sunlight e v entually er ases the de vice . f or maxim um system reliability , these sources should be a v oided. if used in such an en vironment, the pac kage windo w should be co v ered b y an opaque substance . upon deliv er y from wsi, or after each er asure , the psd3xx de vice has all bits in the p ad and epr om in the ??or high state . the configur ation bits are in the ??or lo w state . the code , configur ation, and p ad map data are loaded through the procedure of prog r amming inf or mation f or prog r amming the de vice is a v ailab le directly from wsi. please contact y our local sales representativ e . erasur e and pr ogramming
2-65 key features programmable peripheral PSD301 field-programmable microcontroller peripheral o single chip programmable peripheral for microcontroller-based applications o 19 individually configurable i/o pins that can be used as: ? microcontroller i/o port expansion ? programmable address decoder (pad) i/o ? latched address output ? open drain or cmos o two programmable arrays (pad a and pad b) ? total of 40 product terms and up to 12 inputs and 24 outputs ? address decoding up to 1 mb ?logic replacement o ?o glue?microcontroller chip-set ? built-in address latches for multiplexed address/data bus ? non-multiplexed address/data bus mode ? selectable 8 or 16 bit data bus width ? ale and reset polarity programmable ? selectable modes for read and write control bus as rd/wr or r/w/e ? bhe pin for byte select in 16-bit mode ? psen pin for 8051 users o 256 kbits of uv eprom ? configurable as 32k x 8 or as 16k x 16 ? divides into 8 equal mappable blocks for optimized mapping ? block resolution is 4k x 8 or 2k x 16 ? 70 ns eprom access time, including input latches and pad address decoding. o 16 kbit static ram ? configurable as 2k x 8 or as 1k x 16 ? 70 ns sram access time, including input latches and pad address decoding o address/data track mode ? enables easy interface to shared resources (e.g., mail box sram) with other microcontrollers or a host processor o built-in security ? locks the PSD301 and pad decoding configuration o available in a choice of packages ? 44 pin pldcc, cldcc and tqfp ? 52 pin pqfp ? 44 pin cpga o simple menu-driven software: configure the PSD301 on an ibm pc o pin and function compatible with the psd302 /302l, psd303/303l and psd304r/314rl
psd3xx family 2-66 44-pin 44-pin 44-pin 52-pin pin name pldcc/cldcc cpga tqfp pqfp package package package package (note 58) bhe/psen 1 a 5 39 46 wr/v pp or r/w 2 a 4 40 47 reset 3 b 4 41 48 pb7 4 a 3 42 49 pb6 5 b 3 43 50 pb5 6 a 2 44 51 pb4 7 b 2 1 2 pb3 8 b 1 2 3 pb2 9 c 2 3 4 pb1 10 c 1 4 5 pb0 11 d 2 5 6 gnd 12 d 1 6 7 ale or as 13 e 1 7 8 p a7 14 e 2 8 9 p a6 15 f 1 9 10 p a5 16 f 2 10 11 p a4 17 g 1 11 12 p a3 18 g 2 12 15 p a2 19 h 2 13 16 p a1 20 g 3 14 17 p a0 21 h 3 15 18 rd/e 22 g 4 16 19 ad0/a0 23 h 4 17 20 ad1/a1 24 h 5 18 21 ad2/a2 25 g 5 19 22 ad3/a3 26 h 6 20 23 ad4/a4 27 g 6 21 24 ad5/a5 28 h 7 22 25 ad6/a6 29 g 7 23 28 ad7/a7 30 g 8 24 29 ad8/a8 31 f 7 25 30 ad9/a9 32 f 8 26 31 ad10/a10 33 e 7 27 32 gnd 34 e 8 28 33 ad11/a11 35 d 8 29 34 ad12/a12 36 d 7 30 35 ad13/a13 37 c 8 31 36 ad14/a14 38 c 7 32 37 ad15/a15 39 b 8 33 38 pc0 40 b 7 34 41 pc1 41 a 7 35 42 pc2 42 b 6 36 43 a19/csi 43 a 6 37 44 v cc 44 b 5 38 45 PSD301 pin assignments no te: 58. pins 1, 13, 14, 26, 27, 39, 40, and 52 are no connect.
psd3xx family figur e 42. drawing u1 44 pin plastic thin quad flatpack (tqfp) (package t ype u) 39 ad15/a15 38 ad14/a14 37 ad13/a13 36 ad12/a12 35 ad11/a11 34 gnd 33 ad10/a10 32 ad9/a9 31 ad8/a8 30 ad7/a7 29 ad6/a6 pb4 7 pb3 8 pb2 9 pb1 10 pb0 11 gnd 12 ale or as 13 pa7 14 pa6 15 pa5 16 pa4 17 pa3 18 pa2 19 pa1 20 pa0 21 rd/e 22 ad0/a0 23 ad1/a1 24 ad2/a2 25 ad3/a3 26 ad4/a4 27 ad5/a5 28 6 pb5 5 pb6 4 pb7 3 reset 2 wr/v or r/w 1 bhe/psen 44 v 43 a19/csi 42 pc2 41 pc1 40 pc0 pp cc pb4 pb3 pb2 pb1 pb0 gnd ale or as pa7 pa6 pa5 pa4 ad15/a15 ad14/a14 ad13/a13 ad12/a12 ad11/a11 gnd ad10/a10 ad9/a9 ad8/a8 ad7/a7 ad6/a6 1 2 3 4 5 6 7 8 9 10 11 33 32 31 30 29 28 27 26 25 24 23 12 13 14 15 16 17 18 19 20 21 22 pa3 pa2 pa1 pa0 rd/e ad0/a0 ad1/a1 ad2/a2 ad3/a3 ad4/a4 ad5/a5 pb5 pb6 pb7 reset wr/v pp or r/w bhe/psen v c c a19/csi pc2 pc1 pc0 44 43 42 41 40 39 38 37 36 35 34 (t op view) (t op view) PSD301 package infor mation figur e 41. drawing l4 44 pin ceramic leaded chip car rier (cldcc) with w indow (package t ype l) or drawing j2 44 pin plastic leaded chip car rier (pldcc) without w indow (package t ype j) 2-67
psd3xx family 2-68 39 nc 38 ad15/a15 37 ad14/a14 36 ad13/a13 35 ad12/a12 34 ad11/a11 33 gnd 32 ad10/a10 31 ad9/a9 30 ad8/a8 29 ad7/a7 28 ad6/a6 27 nc nc 1 pb4 2 pb3 3 pb2 4 pb1 5 pb0 6 gnd 7 ale or as 8 pa7 9 pa6 10 pa5 11 pa4 12 nc 13 nc 14 pa3 15 pa2 16 pa1 17 pa0 18 rd/e 19 ad0/a0 20 ad1/a1 21 ad2/a2 22 ad3/a3 23 ad4/a4 24 ad5/a5 25 nc 26 52 nc 51 pb5 50 pb6 49 pb7 48 reset 47 wr/v or r/w 46 bhe/psen 45 v 44 a19/csi 43 pc2 42 pc1 41 pc0 40 nc pp cc (t op view) figur e 44. drawing x2 44 pin cpga (package t ype x) 1 2 3 4 5 6 7 8 a b c d e f g h (t op view , thr ough p a cka ge) PSD301 package infor mation figur e 43. drawing q2 52 pin pqfp (package t ype q)
2-69 key features programmable peripheral psd311 field-programmable microcontroller peripheral o single chip programmable peripheral for microcontroller-based applications o 19 individually configurable i/o pins that can be used as: ? microcontroller i/o port expansion ? programmable address decoder (pad) i/o ? latched address output ? open drain or cmos o two programmable arrays (pad a and pad b) ? total of 40 product terms and up to 12 inputs and 24 outputs ? address decoding up to 1 mb ?logic replacement o ?o glue?microcontroller chip-set ? built-in address latches for multiplexed address/data bus ? non-multiplexed address/data bus mode ? 8-bit data bus width ? ale and reset polarity programmable ? selectable modes for read and write control bus as rd/wr or r/w/e ? psen pin for 8051 users o 256 kbits of uv eprom ? configurable as 32k x 8 ? divides into 8 equal mappable blocks for optimized mapping ? block resolution is 4k x 8 ? 70 ns eprom access time, including input latches and pad address decoding. o 16 kbit static ram ? configurable as 2k x 8 ? 70 ns sram access time, including input latches and pad address decoding o address/data track mode ? enables easy interface to shared resources (e.g., mail box sram) with other microcontrollers or a host processor o built-in security ? locks the psd311 and pad decoding configuration o available in a choice of packages ? 44 pin pldcc, cldccand tqfp ? 52 pin pqfp o simple menu-driven software: configure the psd311 on an ibm pc o pin and function compatible with the psd312 /312l, psd313/313l and psd314r/314rl
psd3xx family 2-70 44-pin 44-pin 52-pin pin name pldcc/cldcc tqfp pqfp package package package ( note 59) psen 1 39 46 wr/v pp or r/w 2 40 47 reset 3 41 48 pb7 4 42 49 pb6 5 43 50 pb5 6 44 51 pb4 7 1 2 pb3 8 2 3 pb2 9 3 4 pb1 10 4 5 pb0 11 5 6 gnd 12 6 7 ale or as 13 7 8 p a7 14 8 9 p a6 15 9 10 p a5 16 10 11 p a4 17 11 12 p a3 18 12 15 p a2 19 13 16 p a1 20 14 17 p a0 21 15 18 rd/e 22 16 19 ad0/a0 23 17 20 ad1/a1 24 18 21 ad2/a2 25 19 22 ad3/a3 26 20 23 ad4/a4 27 21 24 ad5/a5 28 22 25 ad6/a6 29 23 28 ad7/a7 30 24 29 a8 31 25 30 a9 32 26 31 a10 33 27 32 gnd 34 28 33 a11 35 29 34 a12 36 30 35 a13 37 31 36 a14 38 32 37 a15 39 33 38 pc0 40 34 41 pc1 41 35 42 pc2 42 36 43 a19/csi 43 37 44 v cc 44 38 45 psd311 pin assignments no te: 59. pins 1, 13, 14, 26, 27, 39, 40, and 52 are no connect.
psd3xx family figur e 46. drawing u1 44 pin plastic thin quad flatpack (tqfp) (package t ype u) 39 a15 38 a14 37 a13 36 a12 35 a11 34 gnd 33 a10 32 a9 31 a8 30 ad7/a7 29 ad6/a6 pb4 7 pb3 8 pb2 9 pb1 10 pb0 11 gnd 12 ale or as 13 pa7 14 pa6 15 pa5 16 pa4 17 pa3 18 pa2 19 pa1 20 pa0 21 rd/e 22 ad0/a0 23 ad1/a1 24 ad2/a2 25 ad3/a3 26 ad4/a4 27 ad5/a5 28 6 pb5 5 pb6 4 pb7 3 reset 2 wr/v or r/w 1 psen 44 v 43 a19/csi 42 pc2 41 pc1 40 pc0 pp cc pb4 pb3 pb2 pb1 pb0 gnd ale or as pa7 pa6 pa5 pa4 a15 a14 a13 a12 a11 gnd a10 a9 a8 ad7/a7 ad6/a6 1 2 3 4 5 6 7 8 9 10 11 33 32 31 30 29 28 27 26 25 24 23 12 13 14 15 16 17 18 19 20 21 22 pa3 pa2 pa1 pa0 rd/e ad0/a0 ad1/a1 ad2/a2 ad3/a3 ad4/a4 ad5/a5 pb5 pb6 pb7 reset wr/v pp or r/w psen v c c a19/csi pc2 pc1 pc0 44 43 42 41 40 39 38 37 36 35 34 (t op view) (t op view) psd311 package infor mation figur e 45. drawing l4 44 pin ceramic leaded chip car rier (cldcc) with w indow (package t ype l) or drawing j2 44 pin plastic leaded chip car rier (pldcc) without w indow (package t ype j) 2-71
psd3xx family 2-72 psd311 package infor mation figur e 47. drawing q2 52 pin pqfp (package t ype q) 39 nc 38 a15 37 a14 36 a13 35 a12 34 a11 33 gnd 32 a10 31 a9 30 a8 29 ad7/a7 28 ad6/a6 27 nc nc 1 pb4 2 pb3 3 pb2 4 pb1 5 pb0 6 gnd 7 ale or as 8 pa7 9 pa6 10 pa5 11 pa4 12 nc 13 nc 14 pa3 15 pa2 16 pa1 17 pa0 18 rd/e 19 ad0/a0 20 ad1/a1 21 ad2/a2 22 ad3/a3 23 ad4/a4 24 ad5/a5 25 nc 26 52 nc 51 pb5 50 pb6 49 pb7 48 reset 47 wr/v or r/w 46 psen 45 v 44 a19/csi 43 pc2 42 pc1 41 pc0 40 nc pp cc (t op view)
2-73 key features programmable peripheral psd302 field-programmable microcontroller peripheral o single chip programmable peripheral for microcontroller-based applications o 19 individually configurable i/o pins that can be used as: ? microcontroller i/o port expansion ? programmable address decoder (pad) i/o ? latched address output ? open drain or cmos o two programmable arrays (pad a & pad b) ? total of 40 product terms and up to 16 inputs and 24 outputs ? direct address decoding up to 1 meg address space and up to 16 meg with paging ?logic replacement o ?o glue?microcontroller chip-set ? built-in address latches for multiplexed address/data bus ? non-multiplexed address/data bus mode ? selectable 8 or 16 bit data bus width ? ale and reset polarity programmable ? selectable modes for read and write control bus as rd/wr, r/w/e, or r/w/ds ? bhe pin for byte select in 16-bit mode ? psen pin for 8051 users o built-in page logic ? to expand the address space of microcontrollers with limited address space capabilities ? up to 16 pages o 512 kbits of uv eprom ? configurable as 64k x 8 or as 32k x 16 ? divides into 8 equal mappable blocks for optimized mapping ? block resolution is 8k x 8 or 4k x 16 ? 70 ns eprom access time, including input latches and pad address decoding. o 16 kbit static ram ? configurable as 2k x 8 or as 1k x 16 ? 70 ns sram access time, including input latches and pad address decoding o address/data track mode ? enables easy interface to shared resources (e.g., mail box sram) with other microcontrollers or a host processor o cmiser-bit ? programmable option to further reduce power consumption o built-in security ? locks the psd302 and pad decoding configuration o available in a choice of packages ? 44 pin pldcc, cldcc and tqfp ? 52 pin pqfp ? 44 pin cpga o simple menu-driven software: configure the psd302 on an ibm pc o pin and function compatible with the PSD301/301l, psd303/303l and psd304r/304rl
psd3xx family 2-74 psd302 pin assignments 44-pin 44-pin 44-pin 52-pin pin name pldcc/cldcc cpga tqfp pqfp package package package package (note 60) bhe/psen 1 a 5 39 46 wr/v pp or r/w 2 a 4 40 47 reset 3 b 4 41 48 pb7 4 a 3 42 49 pb6 5 b 3 43 50 pb5 6 a 2 44 51 pb4 7 b 2 1 2 pb3 8 b 1 2 3 pb2 9 c 2 3 4 pb1 10 c 1 4 5 pb0 11 d 2 5 6 gnd 12 d 1 6 7 ale or as 13 e 1 7 8 p a7 14 e 2 8 9 p a6 15 f 1 9 10 p a5 16 f 2 10 11 p a4 17 g 1 11 12 p a3 18 g 2 12 15 p a2 19 h 2 13 16 p a1 20 g 3 14 17 p a0 21 h 3 15 18 rd/e/ds 22 g 4 16 19 ad0/a0 23 h 4 17 20 ad1/a1 24 h 5 18 21 ad2/a2 25 g 5 19 22 ad3/a3 26 h 6 20 23 ad4/a4 27 g 6 21 24 ad5/a5 28 h 7 22 25 ad6/a6 29 g 7 23 28 ad7/a7 30 g 8 24 29 ad8/a8 31 f 7 25 30 ad9/a9 32 f 8 26 31 ad10/a10 33 e 7 27 32 gnd 34 e 8 28 33 ad11/a11 35 d 8 29 34 ad12/a12 36 d 7 30 35 ad13/a13 37 c 8 31 36 ad14/a14 38 c 7 32 37 ad15/a15 39 b 8 33 38 pc0 40 b 7 34 41 pc1 41 a 7 35 42 pc2 42 b 6 36 43 a19/csi 43 a 6 37 44 v cc 44 b 5 38 45 no te: 60. pins 1, 13, 14, 26, 27, 39, 40, and 52 are no connect.
psd3xx family 2-75 figur e 49. drawing u1 44 pin plastic thin quad flatpack (tqfp) (package t ype u) 39 ad15/a15 38 ad14/a14 37 ad13/a13 36 ad12/a12 35 ad11/a11 34 gnd 33 ad10/a10 32 ad9/a9 31 ad8/a8 30 ad7/a7 29 ad6/a6 pb4 7 pb3 8 pb2 9 pb1 10 pb0 11 gnd 12 ale or as 13 pa7 14 pa6 15 pa5 16 pa4 17 pa3 18 pa2 19 pa1 20 pa0 21 rd/e/ds 22 ad0/a0 23 ad1/a1 24 ad2/a2 25 ad3/a3 26 ad4/a4 27 ad5/a5 28 6 pb5 5 pb6 4 pb7 3 reset 2 wr/v or r/w 1 bhe/psen 44 v 43 a19/csi 42 pc2 41 pc1 40 pc0 pp cc pb4 pb3 pb2 pb1 pb0 gnd ale or as pa7 pa6 pa5 pa4 ad15/a15 ad14/a14 ad13/a13 ad12/a12 ad11/a11 gnd ad10/a10 ad9/a9 ad8/a8 ad7/a7 ad6/a6 1 2 3 4 5 6 7 8 9 10 11 33 32 31 30 29 28 27 26 25 24 23 12 13 14 15 16 17 18 19 20 21 22 pa3 pa2 pa1 pa0 rd/e/ds ad0/a0 ad1/a1 ad2/a2 ad3/a3 ad4/a4 ad5/a5 pb5 pb6 pb7 reset wr/v pp or r/w bhe/psen v c c a19/csi pc2 pc1 pc0 44 43 42 41 40 39 38 37 36 35 34 (t op view) (t op view) psd302 package infor mation figur e 48. drawing l4 44 pin ceramic leaded chip car rier (cldcc) with w indow (package t ype l) or drawing j2 44 pin plastic leaded chip car rier (pldcc) without w indow (package t ype j)
psd3xx family 2-76 psd302 package infor mation figur e 50. drawing q2 52 pin pqfp (package t ype q) 39 nc 38 ad15/a15 37 ad14/a14 36 ad13/a13 35 ad12/a12 34 ad11/a11 33 gnd 32 ad10/a10 31 ad9/a9 30 ad8/a8 29 ad7/a7 28 ad6/a6 27 nc nc 1 pb4 2 pb3 3 pb2 4 pb1 5 pb0 6 gnd 7 ale or as 8 pa7 9 pa6 10 pa5 11 pa4 12 nc 13 nc 14 pa3 15 pa2 16 pa1 17 pa0 18 rd/e/ds 19 ad0/a0 20 ad1/a1 21 ad2/a2 22 ad3/a3 23 ad4/a4 24 ad5/a5 25 nc 26 52 nc 51 pb5 50 pb6 49 pb7 48 reset 47 wr/v or r/w 46 bhe/psen 45 v 44 a19/csi 43 pc2 42 pc1 41 pc0 40 nc pp cc (t op view) figur e 51. drawing x2 44 pin cpga (package t ype x) 1 2 3 4 5 6 7 8 a b c d e f g h (t op view , thr ough p a cka ge)
2-77 key features programmable peripheral psd312 field-programmable microcontroller peripheral o single chip programmable peripheral for microcontroller-based applications o 19 individually configurable i/o pins that can be used as: ? microcontroller i/o port expansion ? programmable address decoder (pad) i/o ? latched address output ? open drain or cmos o two programmable arrays (pad a & pad b) ? total of 40 product terms and up to 16 inputs and 24 outputs ? direct address decoding up to 1 meg address space and up to 16 meg with paging ?logic replacement o ?o glue?microcontroller chip-set ? built-in address latches for multiplexed address/data bus ? non-multiplexed address/data bus mode ? 8-bit data bus width ? ale and reset polarity programmable ? selectable modes for read and write control bus as rd/wr, r/w/e, or r/w/ds ? psen pin for 8051 users o built-in page logic ? to expand the address space of microcontrollers with limited address space capabilities ? up to 16 pages o 512 kbits of uv eprom ? configured as 64k x 8 ? divides into 8 equal mappable blocks for optimized mapping ? block resolution is 8k x 8 ? 70 ns eprom access time, including input latches and pad address decoding. o 16 kbit static ram ? configured as 2k x 8 ? 70 ns sram access time, including input latches and pad address decoding o address/data track mode ? enables easy interface to shared resources (e.g., mail box sram) with other microcontrollers or a host processor o cmiser-bit ? programmable option to further reduce power consumption o built-in security ? locks the psd312 and pad decoding configuration o available in a choice of packages ? 44 pin pldcc, cldcc and tqfp ? 52 pin pqfp o simple menu-driven software: configure the psd312 on an ibm pc o pin and function compatible with the psd311/311l, psd313/313l and psd314r/314rl
psd3xx family 2-78 psd312 pin assignments 44-pin 44-pin 52-pin pin name pldcc/cldcc tqfp pqfp package package package ( note 61) psen 1 39 46 wr/v pp or r/w 2 40 47 reset 3 41 48 pb7 4 42 49 pb6 5 43 50 pb5 6 44 51 pb4 7 1 2 pb3 8 2 3 pb2 9 3 4 pb1 10 4 5 pb0 11 5 6 gnd 12 6 7 ale or as 13 7 8 p a7 14 8 9 p a6 15 9 10 p a5 16 10 11 p a4 17 11 12 p a3 18 12 15 p a2 19 13 16 p a1 20 14 17 p a0 21 15 18 rd/e/ds 22 16 19 ad0/a0 23 17 20 ad1/a1 24 18 21 ad2/a2 25 19 22 ad3/a3 26 20 23 ad4/a4 27 21 24 ad5/a5 28 22 25 ad6/a6 29 23 28 ad7/a7 30 24 29 a8 31 25 30 a9 32 26 31 a10 33 27 32 gnd 34 28 33 a11 35 29 34 a12 36 30 35 a13 37 31 36 a14 38 32 37 a15 39 33 38 pc0 40 34 41 pc1 41 35 42 pc2 42 36 43 a19/csi 43 37 44 v cc 44 38 45 no te: 61. pins 1, 13, 14, 26, 27, 39, 40, and 52 are no connect.
psd3xx family 2-79 figur e 53. drawing u1 44 pin plastic thin quad flatpack (tqfp) (package t ype u) 39 a15 38 a14 37 a13 36 a12 35 a11 34 gnd 33 a10 32 a9 31 a8 30 ad7/a7 29 ad6/a6 pb4 7 pb3 8 pb2 9 pb1 10 pb0 11 gnd 12 ale or as 13 pa7 14 pa6 15 pa5 16 pa4 17 pa3 18 pa2 19 pa1 20 pa0 21 rd/e/ds 22 ad0/a0 23 ad1/a1 24 ad2/a2 25 ad3/a3 26 ad4/a4 27 ad5/a5 28 6 pb5 5 pb6 4 pb7 3 reset 2 wr/v or r/w 1 psen 44 v 43 a19/csi 42 pc2 41 pc1 40 pc0 pp cc pb4 pb3 pb2 pb1 pb0 gnd ale or as pa7 pa6 pa5 pa4 a15 a14 a13 a12 a11 gnd a10 a9 a8 ad7/a7 ad6/a6 1 2 3 4 5 6 7 8 9 10 11 33 32 31 30 29 28 27 26 25 24 23 12 13 14 15 16 17 18 19 20 21 22 pa3 pa2 pa1 pa0 rd/e/ds ad0/a0 ad1/a1 ad2/a2 ad3/a3 ad4/a4 ad5/a5 pb5 pb6 pb7 reset wr/v pp or r/w psen v c c a19/csi pc2 pc1 pc0 44 43 42 41 40 39 38 37 36 35 34 (t op view) (t op view) psd312 package infor mation figur e 52. drawing l4 44 pin ceramic leaded chip car rier (cldcc) with w indow (package t ype l) or drawing j2 44 pin plastic leaded chip car rier (pldcc) without w indow (package t ype j)
psd3xx family 2-80 psd312 package infor mation figur e 54. drawing q2 52 pin pqfp (package t ype q) 39 nc 38 a15 37 a14 36 a13 35 a12 34 a11 33 gnd 32 a10 31 a9 30 a8 29 ad7/a7 28 ad6/a6 27 nc nc 1 pb4 2 pb3 3 pb2 4 pb1 5 pb0 6 gnd 7 ale or as 8 pa7 9 pa6 10 pa5 11 pa4 12 nc 13 nc 14 pa3 15 pa2 16 pa1 17 pa0 18 rd/e/ds 19 ad0/a0 20 ad1/a1 21 ad2/a2 22 ad3/a3 23 ad4/a4 24 ad5/a5 25 nc 26 52 nc 51 pb5 50 pb6 49 pb7 48 reset 47 wr/v or r/w 46 psen 45 v 44 a19/csi 43 pc2 42 pc1 41 pc0 40 nc pp cc (t op view)
2-81 key features programmable peripheral psd303 field-programmable microcontroller peripheral o single chip programmable peripheral for microcontroller-based applications o 19 individually configurable i/o pins that can be used as: ? microcontroller i/o port expansion ? programmable address decoder (pad) i/o ? latched address output ? open drain or cmos o two programmable arrays (pad a & pad b) ? total of 40 product terms and up to 16 inputs and 24 outputs ? direct address decoding up to 1 meg address space and up to 16 meg with paging ?logic replacement o ?o glue?microcontroller chip-set ? built-in address latches for multiplexed address/data bus ? non-multiplexed address/data bus mode ? selectable 8 or 16 bit data bus width ? ale and reset polarity programmable ? selectable modes for read and write control bus as rd/wr, r/w/e, or r/w/ds ? bhe pin for byte select in 16-bit mode ? psen pin for 8051 users o built-in page logic ? to expand the address space of microcontrollers with limited address space capabilities ? up to 16 pages o 1 m bit of uv eprom ? configurable as 128k x 8 or as 64k x 16 ? divides into 8 equal mappable blocks for optimized mapping ? block resolution is 16k x 8 or 8k x 16 ? 70 ns eprom access time, including input latches and pad address decoding. o 16 kbit static ram ? configurable as 2k x 8 or as 1k x 16 ? 70 ns sram access time, including input latches and pad address decoding o address/data track mode ? enables easy interface to shared resources (e.g., mail box sram) with other microcontrollers or a host processor o built-in security ? locks the psd303 and pad decoding configuration o available in a choice of packages ? 44 pin pldcc, cldcc and tqfp ? 44 pin cpga o simple menu-driven software: configure the psd303 on an ibm pc o pin and function compatible with the PSD301/301l, psd302/302l and psd304r/314rl
psd3xx family 2-82 44-pin 44-pin 44-pin pin name pldcc/cldcc cpga tqfp package package package bhe/psen 1 a 5 39 wr/v pp or r/w 2 a 4 40 reset 3 b 4 41 pb7 4 a 3 42 pb6 5 b 3 43 pb5 6 a 2 44 pb4 7 b 2 1 pb3 8 b 1 2 pb2 9 c 2 3 pb1 10 c 1 4 pb0 11 d 2 5 gnd 12 d 1 6 ale or as 13 e 1 7 p a7 14 e 2 8 p a6 15 f 1 9 p a5 16 f 2 10 p a4 17 g 1 11 p a3 18 g 2 12 p a2 19 h 2 13 p a1 20 g 3 14 p a0 21 h 3 15 rd/e/ds 22 g 4 16 ad0/a0 23 h 4 17 ad1/a1 24 h 5 18 ad2/a2 25 g 5 19 ad3/a3 26 h 6 20 ad4/a4 27 g 6 21 ad5/a5 28 h 7 22 ad6/a6 29 g 7 23 ad7/a7 30 g 8 24 ad8/a8 31 f 7 25 ad9/a9 32 f 8 26 ad10/a10 33 e 7 27 gnd 34 e 8 28 ad11/a11 35 d 8 29 ad12/a12 36 d 7 30 ad13/a13 37 c 8 31 ad14/a14 38 c 7 32 ad15/a15 39 b 8 33 pc0 40 b 7 34 pc1 41 a 7 35 pc2 42 b 6 36 a19/csi 43 a 6 37 v cc 44 b 5 38 psd303 pin assignments
psd3xx family 2-83 figur e 56. drawing u1 44 pin plastic thin quad flatpack (tqfp) (package t ype u) 39 ad15/a15 38 ad14/a14 37 ad13/a13 36 ad12/a12 35 ad11/a11 34 gnd 33 ad10/a10 32 ad9/a9 31 ad8/a8 30 ad7/a7 29 ad6/a6 pb4 7 pb3 8 pb2 9 pb1 10 pb0 11 gnd 12 ale or as 13 pa7 14 pa6 15 pa5 16 pa4 17 pa3 18 pa2 19 pa1 20 pa0 21 rd/e/ds 22 ad0/a0 23 ad1/a1 24 ad2/a2 25 ad3/a3 26 ad4/a4 27 ad5/a5 28 6 pb5 5 pb6 4 pb7 3 reset 2 wr/v or r/w 1 bhe/psen 44 v 43 a19/csi 42 pc2 41 pc1 40 pc0 pp cc pb4 pb3 pb2 pb1 pb0 gnd ale or as pa7 pa6 pa5 pa4 ad15/a15 ad14/a14 ad13/a13 ad12/a12 ad11/a11 gnd ad10/a10 ad9/a9 ad8/a8 ad7/a7 ad6/a6 1 2 3 4 5 6 7 8 9 10 11 33 32 31 30 29 28 27 26 25 24 23 12 13 14 15 16 17 18 19 20 21 22 pa3 pa2 pa1 pa0 rd/e/ds ad0/a0 ad1/a1 ad2/a2 ad3/a3 ad4/a4 ad5/a5 pb5 pb6 pb7 reset wr/v pp or r/w bhe/psen v c c a19/csi pc2 pc1 pc0 44 43 42 41 40 39 38 37 36 35 34 (t op view) (t op view) psd303 package infor mation figur e 55. drawing l4 44 pin ceramic leaded chip car rier (cldcc) with w indow (package t ype l) or drawing j2 44 pin plastic leaded chip car rier (pldcc) without w indow (package t ype j)
psd3xx family 2-84 psd303 package infor mation figur e 57. drawing x2 44 pin cpga (package t ype x) 1 2 3 4 5 6 7 8 a b c d e f g h (t op view , thr ough p a cka ge)
2-85 key features programmable peripheral psd313 field-programmable microcontroller peripheral o single chip programmable peripheral for microcontroller-based applications o 19 individually configurable i/o pins that can be used as: ? microcontroller i/o port expansion ? programmable address decoder (pad) i/o ? latched address output ? open drain or cmos o two programmable arrays (pad a & pad b) ? total of 40 product terms and up to 16 inputs and 24 outputs ? direct address decoding up to 1 meg address space and up to 16 meg with paging ?logic replacement o ?o glue?microcontroller chip-set ? built-in address latches for multiplexed address/data bus ? non-multiplexed address/data bus mode ? 8-bit data bus width ? ale and reset polarity programmable ? selectable modes for read and write control bus as rd/wr, r/w/e, or r/w/ds ? psen pin for 8051 users o built-in page logic ? to expand the address space of microcontrollers with limited address space capabilities ? up to 16 pages o 1 m bit of uv eprom ? configurable as 128k x 8 ? divides into 8 equal mappable blocks for optimized mapping ? block resolution is 16k x 8 ? 70 ns eprom access time, including input latches and pad address decoding. o 16 kbit static ram ? configurable as 2k x 8 ? 70 ns sram access time, including input latches and pad address decoding o address/data track mode ? enables easy interface to shared resources (e.g., mail box sram) with other microcontrollers or a host processor o built-in security ? locks the psd313 and pad decoding configuration o available in a choice of packages ? 44 pin pldcc, cldcc and tqfp ? 52 pin pqfp o simple menu-driven software: configure the psd313 on an ibm pc o pin and function compatible with the psd311/311l, psd312/312l and psd314r/314rl
psd3xx family 2-86 psd313 pin assignments 44-pin 44-pin 52-pin pin name pldcc/cldcc tqfp pqfp package package package ( note 62) psen 1 39 46 wr/v pp or r/w 2 40 47 reset 3 41 48 pb7 4 42 49 pb6 5 43 50 pb5 6 44 51 pb4 7 1 2 pb3 8 2 3 pb2 9 3 4 pb1 10 4 5 pb0 11 5 6 gnd 12 6 7 ale or as 13 7 8 p a7 14 8 9 p a6 15 9 10 p a5 16 10 11 p a4 17 11 12 p a3 18 12 15 p a2 19 13 16 p a1 20 14 17 p a0 21 15 18 rd/e/ds 22 16 19 ad0/a0 23 17 20 ad1/a1 24 18 21 ad2/a2 25 19 22 ad3/a3 26 20 23 ad4/a4 27 21 24 ad5/a5 28 22 25 ad6/a6 29 23 28 ad7/a7 30 24 29 a8 31 25 30 a9 32 26 31 a10 33 27 32 gnd 34 28 33 a11 35 29 34 a12 36 30 35 a13 37 31 36 a14 38 32 37 a15 39 33 38 pc0 40 34 41 pc1 41 35 42 pc2 42 36 43 a19/csi 43 37 44 v cc 44 38 45 no te: 62. pins 1, 13, 14, 26, 27, 39, 40, and 52 are no connect.
psd3xx family 2-87 figur e 59. drawing u1 44 pin plastic thin quad flatpack (tqfp) (package t ype u) 39 a15 38 a14 37 a13 36 a12 35 a11 34 gnd 33 a10 32 a9 31 a8 30 ad7/a7 29 ad6/a6 pb4 7 pb3 8 pb2 9 pb1 10 pb0 11 gnd 12 ale or as 13 pa7 14 pa6 15 pa5 16 pa4 17 pa3 18 pa2 19 pa1 20 pa0 21 rd/e/ds 22 ad0/a0 23 ad1/a1 24 ad2/a2 25 ad3/a3 26 ad4/a4 27 ad5/a5 28 6 pb5 5 pb6 4 pb7 3 reset 2 wr/v or r/w 1 psen 44 v 43 a19/csi 42 pc2 41 pc1 40 pc0 pp cc pb4 pb3 pb2 pb1 pb0 gnd ale or as pa7 pa6 pa5 pa4 a15 a14 a13 a12 a11 gnd a10 a9 a8 ad7/a7 ad6/a6 1 2 3 4 5 6 7 8 9 10 11 33 32 31 30 29 28 27 26 25 24 23 12 13 14 15 16 17 18 19 20 21 22 pa3 pa2 pa1 pa0 rd/e/ds ad0/a0 ad1/a1 ad2/a2 ad3/a3 ad4/a4 ad5/a5 pb5 pb6 pb7 reset wr/v pp or r/w psen v c c a19/csi pc2 pc1 pc0 44 43 42 41 40 39 38 37 36 35 34 (t op view) (t op view) psd313 package infor mation figur e 58. drawing l4 44 pin ceramic leaded chip car rier (cldcc) with w indow (package t ype l) or drawing j2 44 pin plastic leaded chip car rier (pldcc) without w indow (package t ype j)
psd3xx family 2-88 39 nc 38 a15 37 a14 36 a13 35 a12 34 a11 33 gnd 32 a10 31 a9 30 a8 29 ad7/a7 28 ad6/a6 27 nc nc 1 pb4 2 pb3 3 pb2 4 pb1 5 pb0 6 gnd 7 ale or as 8 pa7 9 pa6 10 pa5 11 pa4 12 nc 13 nc 14 pa3 15 pa2 16 pa1 17 pa0 18 rd/e/ds 19 ad0/a0 20 ad1/a1 21 ad2/a2 22 ad3/a3 23 ad4/a4 24 ad5/a5 25 nc 26 52 nc 51 pb5 50 pb6 49 pb7 48 reset 47 wr/v or r/w 46 psen 45 v 44 a19/csi 43 pc2 42 pc1 41 pc0 40 nc pp cc psd313 package infor mation figur e 60. drawing q2 52 pin pqfp (package t ype q) (t op view)
2-89 key features programmable peripheral psd304r field-programmable microcontroller peripheral o single chip programmable peripheral for microcontroller-based applications o 19 individually configurable i/o pins that can be used as: ? microcontroller i/o port expansion ? programmable address decoder (pad) i/o ? latched address output ? open drain or cmos o two programmable arrays (pad a & pad b) ? total of 40 product terms and up to 16 inputs and 24 outputs ? direct address decoding up to 1 meg address space and up to 16 meg with paging ?logic replacement o ?o glue?microcontroller chip-set ? built-in address latches for multiplexed address/data bus ? non-multiplexed address/data bus mode ? selectable 8 or 16 bit data bus width ? ale and reset polarity programmable ? selectable modes for read and write control bus as rd/wr, r/w/e, or r/w/ds ? bhe pin for byte select in 16-bit mode ? psen pin for 8051 users o built-in page logic ? to expand the address space of microcontrollers with limited address space capabilities ? up to 16 pages o 2 m bit of uv eprom ? configurable as 256k x 8 or as 128k x 16 ? divides into 8 equal mappable blocks for optimized mapping ? block resolution is 32k x 8 or 16k x 16 ? 120 ns eprom access time, including input latches and pad address decoding. o address/data track mode ? enables easy interface to shared resources (e.g., mail box sram) with other microcontrollers or a host processor o built-in security ? locks the psd304r and pad decoding configuration o available in a choice of packages ? 44 pin pldcc, cldcc and tqfp ? 44 pin cpga o simple menu-driven software: configure the psd304r on an ibm pc o pin and function compatible with the PSD301/301l, psd302/302l and psd303/303l
psd3xx family 2-90 44-pin 44-pin 44-pin pin name pldcc/cldcc cpga tqfp package package package bhe/psen 1 a 5 39 wr/v pp or r/w 2 a 4 40 reset 3 b 4 41 pb7 4 a 3 42 pb6 5 b 3 43 pb5 6 a 2 44 pb4 7 b 2 1 pb3 8 b 1 2 pb2 9 c 2 3 pb1 10 c 1 4 pb0 11 d 2 5 gnd 12 d 1 6 ale or as 13 e 1 7 p a7 14 e 2 8 p a6 15 f 1 9 p a5 16 f 2 10 p a4 17 g 1 11 p a3 18 g 2 12 p a2 19 h 2 13 p a1 20 g 3 14 p a0 21 h 3 15 rd/e/ds 22 g 4 16 ad0/a0 23 h 4 17 ad1/a1 24 h 5 18 ad2/a2 25 g 5 19 ad3/a3 26 h 6 20 ad4/a4 27 g 6 21 ad5/a5 28 h 7 22 ad6/a6 29 g 7 23 ad7/a7 30 g 8 24 ad8/a8 31 f 7 25 ad9/a9 32 f 8 26 ad10/a10 33 e 7 27 gnd 34 e 8 28 ad11/a11 35 d 8 29 ad12/a12 36 d 7 30 ad13/a13 37 c 8 31 ad14/a14 38 c 7 32 ad15/a15 39 b 8 33 pc0 40 b 7 34 pc1 41 a 7 35 pc2 42 b 6 36 a19/csi 43 a 6 37 v cc 44 b 5 38 psd304r pin assignments
psd3xx family 2-91 figur e 62. drawing u1 44 pin plastic thin quad flatpack (tqfp) (package t ype u) 39 ad15/a15 38 ad14/a14 37 ad13/a13 36 ad12/a12 35 ad11/a11 34 gnd 33 ad10/a10 32 ad9/a9 31 ad8/a8 30 ad7/a7 29 ad6/a6 pb4 7 pb3 8 pb2 9 pb1 10 pb0 11 gnd 12 ale or as 13 pa7 14 pa6 15 pa5 16 pa4 17 pa3 18 pa2 19 pa1 20 pa0 21 rd/e/ds 22 ad0/a0 23 ad1/a1 24 ad2/a2 25 ad3/a3 26 ad4/a4 27 ad5/a5 28 6 pb5 5 pb6 4 pb7 3 reset 2 wr/v or r/w 1 bhe/psen 44 v 43 a19/csi 42 pc2 41 pc1 40 pc0 pp cc pb4 pb3 pb2 pb1 pb0 gnd ale or as pa7 pa6 pa5 pa4 ad15/a15 ad14/a14 ad13/a13 ad12/a12 ad11/a11 gnd ad10/a10 ad9/a9 ad8/a8 ad7/a7 ad6/a6 1 2 3 4 5 6 7 8 9 10 11 33 32 31 30 29 28 27 26 25 24 23 12 13 14 15 16 17 18 19 20 21 22 pa3 pa2 pa1 pa0 rd/e/ds ad0/a0 ad1/a1 ad2/a2 ad3/a3 ad4/a4 ad5/a5 pb5 pb6 pb7 reset wr/v pp or r/w bhe/psen v c c a19/csi pc2 pc1 pc0 44 43 42 41 40 39 38 37 36 35 34 (t op view) (t op view) psd304r package infor mation figur e 61. drawing l4 44 pin ceramic leaded chip car rier (cldcc) with w indow (package t ype l) or drawing j2 44 pin plastic leaded chip car rier (pldcc) without w indow (package t ype j)
psd3xx family 2-92 psd304r package infor mation figur e 63. drawing x2 44 pin cpga (package t ype x) 1 2 3 4 5 6 7 8 a b c d e f g h (t op view , thr ough p a cka ge)
2-93 key features programmable peripheral psd314r field-programmable microcontroller peripheral o single chip programmable peripheral for microcontroller-based applications o 19 individually configurable i/o pins that can be used as: ? microcontroller i/o port expansion ? programmable address decoder (pad) i/o ? latched address output ? open drain or cmos o two programmable arrays (pad a & pad b) ? total of 40 product terms and up to 16 inputs and 24 outputs ? direct address decoding up to 1 meg address space and up to 16 meg with paging ?logic replacement o ?o glue?microcontroller chip-set ? built-in address latches for multiplexed address/data bus ? non-multiplexed address/data bus mode ? 8-bit data bus width ? ale and reset polarity programmable ? selectable modes for read and write control bus as rd/wr, r/w/e, or r/w/ds ? psen pin for 8051 users o built-in page logic ? to expand the address space of microcontrollers with limited address space capabilities ? up to 16 pages o 2 m bit of uv eprom ? configurable as 256k x 8 ? divides into 8 equal mappable blocks for optimized mapping ? block resolution is 32k x 8 ? 120 ns eprom access time, including input latches and pad address decoding. o address/data track mode ? enables easy interface to shared resources (e.g., mail box sram) with other microcontrollers or a host processor o built-in security ? locks the psd314r and pad decoding configuration o available in a choice of packages ? 44 pin pldcc, cldcc and tqfp ? 52 pin pqfp o simple menu-driven software: configure the psd314r on an ibm pc o pin and function compatible with the psd311/311l, psd312/312l and psd313/313l
psd3xx family 2-94 psd314r pin assignments 44-pin 44-pin 52-pin pin name pldcc/cldcc tqfp pqfp package package package ( note 63) psen 1 39 46 wr/v pp or r/w 2 40 47 reset 3 41 48 pb7 4 42 49 pb6 5 43 50 pb5 6 44 51 pb4 7 1 2 pb3 8 2 3 pb2 9 3 4 pb1 10 4 5 pb0 11 5 6 gnd 12 6 7 ale or as 13 7 8 p a7 14 8 9 p a6 15 9 10 p a5 16 10 11 p a4 17 11 12 p a3 18 12 15 p a2 19 13 16 p a1 20 14 17 p a0 21 15 18 rd/e/ds 22 16 19 ad0/a0 23 17 20 ad1/a1 24 18 21 ad2/a2 25 19 22 ad3/a3 26 20 23 ad4/a4 27 21 24 ad5/a5 28 22 25 ad6/a6 29 23 28 ad7/a7 30 24 29 a8 31 25 30 a9 32 26 31 a10 33 27 32 gnd 34 28 33 a11 35 29 34 a12 36 30 35 a13 37 31 36 a14 38 32 37 a15 39 33 38 pc0 40 34 41 pc1 41 35 42 pc2 42 36 43 a19/csi 43 37 44 v cc 44 38 45 no te: 63. pins 1, 13, 14, 26, 27, 39, 40, and 52 are no connect.
psd3xx family 2-95 figur e 65. drawing u1 44 pin plastic thin quad flatpack (tqfp) (package t ype u) 39 a15 38 a14 37 a13 36 a12 35 a11 34 gnd 33 a10 32 a9 31 a8 30 ad7/a7 29 ad6/a6 pb4 7 pb3 8 pb2 9 pb1 10 pb0 11 gnd 12 ale or as 13 pa7 14 pa6 15 pa5 16 pa4 17 pa3 18 pa2 19 pa1 20 pa0 21 rd/e/ds 22 ad0/a0 23 ad1/a1 24 ad2/a2 25 ad3/a3 26 ad4/a4 27 ad5/a5 28 6 pb5 5 pb6 4 pb7 3 reset 2 wr/v or r/w 1 psen 44 v 43 a19/csi 42 pc2 41 pc1 40 pc0 pp cc pb4 pb3 pb2 pb1 pb0 gnd ale or as pa7 pa6 pa5 pa4 a15 a14 a13 a12 a11 gnd a10 a9 a8 ad7/a7 ad6/a6 1 2 3 4 5 6 7 8 9 10 11 33 32 31 30 29 28 27 26 25 24 23 12 13 14 15 16 17 18 19 20 21 22 pa3 pa2 pa1 pa0 rd/e/ds ad0/a0 ad1/a1 ad2/a2 ad3/a3 ad4/a4 ad5/a5 pb5 pb6 pb7 reset wr/v pp or r/w psen v c c a19/csi pc2 pc1 pc0 44 43 42 41 40 39 38 37 36 35 34 (t op view) (t op view) psd314r package infor mation figur e 64. drawing l4 44 pin ceramic leaded chip car rier (cldcc) with w indow (package t ype l) or drawing j2 44 pin plastic leaded chip car rier (pldcc) without w indow (package t ype j)
psd3xx family 2-96 39 nc 38 a15 37 a14 36 a13 35 a12 34 a11 33 gnd 32 a10 31 a9 30 a8 29 ad7/a7 28 ad6/a6 27 nc nc 1 pb4 2 pb3 3 pb2 4 pb1 5 pb0 6 gnd 7 ale or as 8 pa7 9 pa6 10 pa5 11 pa4 12 nc 13 nc 14 pa3 15 pa2 16 pa1 17 pa0 18 rd/e/ds 19 ad0/a0 20 ad1/a1 21 ad2/a2 22 ad3/a3 23 ad4/a4 24 ad5/a5 25 nc 26 52 nc 51 pb5 50 pb6 49 pb7 48 reset 47 wr/v or r/w 46 psen 45 v 44 a19/csi 43 pc2 42 pc1 41 pc0 40 nc pp cc psd314r package infor mation figur e 66. drawing q2 52 pin pqfp (package t ype q) (t op view)
2-97 o single chip programmable peripheral for microcontroller-based applications o 3.0 to 5.5 volt operation o 19 individually configurable i/o pins that can be used as: ? microcontroller i/o port expansion ? programmable address decoder (pad) i/o ? latched address output ? open drain or cmos o two programmable arrays (pad a and pad b) ? total of 40 product terms and up to 12 inputs and 24 outputs ? address decoding up to 1 mb ?logic replacement o ?o glue?microcontroller chip-set ? built-in address latches for multiplexed address/data bus ? non-multiplexed address/data bus mode ? selectable 8 or 16 bit data bus width ? ale polarity programmable ? selectable modes for read and write control bus as rd/wr or r/w/e ? bhe pin for byte select in 16-bit mode ? psen pin for 8051 users o 256 kbits of uv eprom ? configurable as 32k x 8 or as 16k x 16 ? divides into 8 equal mappable blocks for optimized mapping ? block resolution is 4k x 8 or 2k x 16 ? 150 ns eprom access time, including input latches and pad address decoding. o 16 kbit static ram ? configurable as 2k x 8 or as 1k x 16 ? 150 ns sram access time, including input latches and pad address decoding o address/data track mode ? enables easy interface to shared resources (e.g., mail box sram) with other microcontrollers or a host processor o built-in security ? locks the PSD301l and pad decoding configuration o available in a choice of packages ? 44 pin pldcc, cldcc and tqfp o simple menu-driven software: configure the PSD301l on an ibm pc o pin compatible with the psd3xx and psd3xxl series key features programmable peripheral PSD301l 3-volt single-chip microcontroller peripheral
psd3xx family 2-98 44-pin 44-pin pin name pldcc/cldcc tqfp package package bhe/psen 1 39 wr/v pp or r/w 2 40 reset 3 41 pb7 4 42 pb6 5 43 pb5 6 44 pb4 7 1 pb3 8 2 pb2 9 3 pb1 10 4 pb0 11 5 gnd 12 6 ale or as 13 7 p a7 14 8 p a6 15 9 p a5 16 10 p a4 17 11 p a3 18 12 p a2 19 13 p a1 20 14 p a0 21 15 rd/e 22 16 ad0/a0 23 17 ad1/a1 24 18 ad2/a2 25 19 ad3/a3 26 20 ad4/a4 27 21 ad5/a5 28 22 ad6/a6 29 23 ad7/a7 30 24 ad8/a8 31 25 ad9/a9 32 26 ad10/a10 33 27 gnd 34 28 ad11/a11 35 29 ad12/a12 36 30 ad13/a13 37 31 ad14/a14 38 32 ad15/a15 39 33 pc0 40 34 pc1 41 35 pc2 42 36 a19/csi 43 37 v cc 44 38 PSD301l pin assignments
psd3xx family 2-99 figur e 68. drawing j2 44 pin plastic leaded chip car rier (pldcc) (package t ype j) 39 ad15/a15 38 ad/14/a14 37 ad13/a13 36 ad12/a12 35 ad11/a11 34 gnd 33 ad10/a10 32 ad9/a9 31 ad8/a8 30 ad7/a7 29 ad6/a6 pb4 7 pb3 8 pb2 9 pb1 10 pb0 11 gnd 12 ale or as 13 pa7 14 pa6 15 pa5 16 pa4 17 pa3 18 pa2 19 pa1 20 pa0 21 rd/e 22 ad0/a0 23 ad1/a1 24 ad2/a2 25 ad3/a3 26 ad4/a4 27 ad5/a5 28 6 pb5 5 pb6 4 pb7 3 reset 2 wr/v or r/w 1 bhe/psen 44 v 43 a19/csi 42 pc2 41 pc1 40 pc0 pp cc 39 ad15/a15 38 ad14/a14 37 ad13/a13 36 ad12/a12 35 ad11/a11 34 gnd 33 ad10/a10 32 ad9/a9 31 ad8/a8 30 ad7/a7 29 ad6/a6 pb4 7 pb3 8 pb2 9 pb1 10 pb0 11 gnd 12 ale or as 13 pa7 14 pa6 15 pa5 16 pa4 17 pa3 18 pa2 19 pa1 20 pa0 21 rd/e 22 ad0/a0 23 ad1/a1 24 ad2/a2 25 ad3/a3 26 ad4/a4 27 ad5/a5 28 6 pb5 5 pb6 4 pb7 3 reset 2 wr/v or r/w 1 bhe/psen 44 v 43 a19/csi 42 pc2 41 pc1 40 pc0 pp cc (t op view) (t op view) PSD301l package infor mation figur e 67. drawing l4 44 pin ceramic leaded chip car rier (cldcc) with w indow (package t ype l)
psd3xx family 2-100 PSD301l package infor mation figur e 69. drawing u1 44 pin plastic thin quad flatpack (tqfp) (package t ype u) pb4 pb3 pb2 pb1 pb0 gnd ale or as pa7 pa6 pa5 pa4 ad15/a15 ad14/a14 ad13/a13 ad12/a12 ad11/a11 gnd ad10/a10 ad9/a9 ad8/a8 ad7/a7 ad6/a6 1 2 3 4 5 6 7 8 9 10 11 33 32 31 30 29 28 27 26 25 24 23 12 13 14 15 16 17 18 19 20 21 22 pa3 pa2 pa1 pa0 rd/e ad0/a0 ad1/a1 ad2/a2 ad3/a3 ad4/a4 ad5/a5 pb5 pb6 pb7 reset wr/v pp or r/w bhe/psen v c c a19/csi pc2 pc1 pc0 44 43 42 41 40 39 38 37 36 35 34 (t op view)
2-101 o single chip programmable peripheral for microcontroller-based applications o 3.0 to 5.5 volt operation o 19 individually configurable i/o pins that can be used as: ? microcontroller i/o port expansion ? programmable address decoder (pad) i/o ? latched address output ? open drain or cmos o two programmable arrays (pad a and pad b) ? total of 40 product terms and up to 12 inputs and 24 outputs ? address decoding up to 1 meg address space ?logic replacement o ?o glue?microcontroller chip-set ? built-in address latches for multiplexed address/data bus ? non-multiplexed address/data bus mode ? 8-bit data bus width ? ale polarity programmable ? selectable modes for read and write control bus as rd/wr or r/w/e ? psen pin for 8051 users o 256 kbits of uv eprom ? organized as 32k x 8 ? divides into 8 equal mappable blocks for optimized mapping ? block resolution is 4k x 8 ? 150 ns eprom access time, including input latches and pad address decoding. o 16 kbit static ram ? organized as 2k x 8 ? 150 ns sram access time, including input latches and pad address decoding o address/data track mode ? enables easy interface to shared resources (e.g., mail box sram) with other microcontrollers or a host processor o built-in security ? locks the psd311l and pad decoding configuration o available in a choice of packages ? 44 pin pldcc, cldcc and tqfp o simple menu-driven software: configure the psd311l on an ibm pc o pin compatible with the psd3xx and psd3xxl series key features programmable peripheral psd311l 3-volt single-chip microcontroller peripheral
psd3xx family 2-102 44-pin 44-pin pin name pldcc/cldcc tqfp package package psen 1 39 wr/v pp or r/w 2 40 reset 3 41 pb7 4 42 pb6 5 43 pb5 6 44 pb4 7 1 pb3 8 2 pb2 9 3 pb1 10 4 pb0 11 5 gnd 12 6 ale or as 13 7 p a7 14 8 p a6 15 9 p a5 16 10 p a4 17 11 p a3 18 12 p a2 19 13 p a1 20 14 p a0 21 15 rd/e 22 16 ad0/a0 23 17 ad1/a1 24 18 ad2/a2 25 19 ad3/a3 26 20 ad4/a4 27 21 ad5/a5 28 22 ad6/a6 29 23 ad7/a7 30 24 a8 31 25 a9 32 26 a10 33 27 gnd 34 28 a11 35 29 a12 36 30 a13 37 31 a14 38 32 a15 39 33 pc0 40 34 pc1 41 35 pc2 42 36 a19/csi 43 37 v cc 44 38 psd311l pin assignments
psd3xx family 2-103 figur e 71. drawing j2 44 pin plastic leaded chip car rier (pldcc) (package t ype j) 39 a15 38 a14 37 a13 36 a12 35 a11 34 gnd 33 a10 32 a9 31 a8 30 ad7/a7 29 ad6/a6 pb4 7 pb3 8 pb2 9 pb1 10 pb0 11 gnd 12 ale or as 13 pa7 14 pa6 15 pa5 16 pa4 17 pa3 18 pa2 19 pa1 20 pa0 21 rd/e 22 ad0/a0 23 ad1/a1 24 ad2/a2 25 ad3/a3 26 ad4/a4 27 ad5/a5 28 6 pb5 5 pb6 4 pb7 3 reset 2 wr/v or r/w 1 psen 44 v 43 a19/csi 42 pc2 41 pc1 40 pc0 pp cc 39 a15 38 a14 37 a13 36 a12 35 a11 34 gnd 33 a10 32 a9 31 a8 30 ad7/a7 29 ad6/a6 pb4 7 pb3 8 pb2 9 pb1 10 pb0 11 gnd 12 ale or as 13 pa7 14 pa6 15 pa5 16 pa4 17 pa3 18 pa2 19 pa1 20 pa0 21 rd/e 22 ad0/a0 23 ad1/a1 24 ad2/a2 25 ad3/a3 26 ad4/a4 27 ad5/a5 28 6 pb5 5 pb6 4 pb7 3 reset 2 wr/v or r/w 1 psen 44 v 43 a19/csi 42 pc2 41 pc1 40 pc0 pp cc (t op view) (t op view) psd311l package infor mation figur e 70. drawing l4 44 pin ceramic leaded chip car rier (cldcc) with w indow (package t ype l)
psd3xx family 2-104 psd311l package infor mation figur e 72. drawing u1 44 pin plastic thin quad flatpack (tqfp) (package t ype u) pb4 pb3 pb2 pb1 pb0 gnd ale or as pa7 pa6 pa5 pa4 a15 a14 a13 a12 a11 gnd a10 a9 a8 ad7/a7 ad6/a6 1 2 3 4 5 6 7 8 9 10 11 33 32 31 30 29 28 27 26 25 24 23 12 13 14 15 16 17 18 19 20 21 22 pa3 pa2 pa1 pa0 rd/e ad0/a0 ad1/a1 ad2/a2 ad3/a3 ad4/a4 ad5/a5 pb5 pb6 pb7 reset wr/v pp or r/w psen v c c a19/csi pc2 pc1 pc0 44 43 42 41 40 39 38 37 36 35 34 (t op view)
2-105 o single chip programmable peripheral for microcontroller-based applications o 3.0 to 5.5 volt operation o 19 individually configurable i/o pins that can be used as: ? microcontroller i/o port expansion ? programmable address decoder (pad) i/o ? latched address output ? open drain or cmos o two programmable arrays (pad a & pad b) ? total of 40 product terms and up to 16 inputs and 24 outputs ? direct address decoding up to 1 meg address space and up to 16 meg with paging ?logic replacement o ?o glue?microcontroller chip-set ? built-in address latches for multiplexed address/data bus ? non-multiplexed address/data bus mode ? selectable 8 or 16 bit data bus width ? ale polarity programmable ? selectable modes for read and write control bus as rd/wr, r/w/e, or r/w/ds ? bhe pin for byte select in 16-bit mode ? psen pin for 8051 users o built-in page logic ? to expand the address space of microcontrollers with limited address space capabilities ? up to 16 pages o 512 kbits of uv eprom ? configurable as 64k x 8 or as 32k x 16 ? divides into 8 equal mappable blocks for optimized mapping ? block resolution is 8k x 8 or 4k x 16 ? 150 ns eprom access time, including input latches and pad address decoding. o 16 kbit static ram ? configurable as 2k x 8 or as 1k x 16 ? 150 ns sram access time, including input latches and pad address decoding o address/data track mode ? enables easy interface to shared resources (e.g., mail box sram) with other microcontrollers or a host processor o cmiser-bit ? programmable option to further reduce power consumption o built-in security ? locks the psd302l and pad decoding configuration o available in a choice of packages ? 44 pin pldcc, cldcc and tqfp o simple menu-driven software: configure the psd302l on an ibm pc o pin and functionally compatible with the psd3xx and psd3xxl series key features programmable peripheral psd302l 3-volt single-chip microcontroller peripheral
psd3xx family 2-106 44-pin 44-pin pin name pldcc/cldcc tqfp package package bhe/psen 1 39 wr/v pp or r/w 2 40 reset 3 41 pb7 4 42 pb6 5 43 pb5 6 44 pb4 7 1 pb3 8 2 pb2 9 3 pb1 10 4 pb0 11 5 gnd 12 6 ale or as 13 7 p a7 14 8 p a6 15 9 p a5 16 10 p a4 17 11 p a3 18 12 p a2 19 13 p a1 20 14 p a0 21 15 rd/e/ds 22 16 ad0/a0 23 17 ad1/a1 24 18 ad2/a2 25 19 ad3/a3 26 20 ad4/a4 27 21 ad5/a5 28 22 ad6/a6 29 23 ad7/a7 30 24 ad8/a8 31 25 ad9/a9 32 26 ad10/a10 33 27 gnd 34 28 ad11/a11 35 29 ad12/a12 36 30 ad13/a13 37 31 ad14/a14 38 32 ad15/a15 39 33 pc0 40 34 pc1 41 35 pc2 42 36 a19/csi 43 37 v cc 44 38 psd302l pin assignments
psd3xx family 2-107 figur e 74. drawing j2 44 pin plastic leaded chip car rier (pldcc) (package t ype j) 39 ad15/a15 38 ad/14/a14 37 ad13/a13 36 ad12/a12 35 ad11/a11 34 gnd 33 ad10/a10 32 ad9/a9 31 ad8/a8 30 ad7/a7 29 ad6/a6 pb4 7 pb3 8 pb2 9 pb1 10 pb0 11 gnd 12 ale or as 13 pa7 14 pa6 15 pa5 16 pa4 17 pa3 18 pa2 19 pa1 20 pa0 21 rd/e/ds 22 ad0/a0 23 ad1/a1 24 ad2/a2 25 ad3/a3 26 ad4/a4 27 ad5/a5 28 6 pb5 5 pb6 4 pb7 3 reset 2 wr/v or r/w 1 bhe/psen 44 v 43 a19/csi 42 pc2 41 pc1 40 pc0 pp cc 39 ad15/a15 38 ad14/a14 37 ad13/a13 36 ad12/a12 35 ad11/a11 34 gnd 33 ad10/a10 32 ad9/a9 31 ad8/a8 30 ad7/a7 29 ad6/a6 pb4 7 pb3 8 pb2 9 pb1 10 pb0 11 gnd 12 ale or as 13 pa7 14 pa6 15 pa5 16 pa4 17 pa3 18 pa2 19 pa1 20 pa0 21 rd/e/ds 22 ad0/a0 23 ad1/a1 24 ad2/a2 25 ad3/a3 26 ad4/a4 27 ad5/a5 28 6 pb5 5 pb6 4 pb7 3 reset 2 wr/v or r/w 1 bhe/psen 44 v 43 a19/csi 42 pc2 41 pc1 40 pc0 pp cc (t op view) (t op view) psd302l package infor mation figur e 73. drawing l4 44 pin ceramic leaded chip car rier (cldcc) with w indow (package t ype l)
psd3xx family 2-108 psd302l package infor mation figur e 75. drawing u1 44 pin plastic thin quad flatpack (tqfp) (package t ype u) pb4 pb3 pb2 pb1 pb0 gnd ale or as pa7 pa6 pa5 pa4 ad15/a15 ad14/a14 ad13/a13 ad12/a12 ad11/a11 gnd ad10/a10 ad9/a9 ad8/a8 ad7/a7 ad6/a6 1 2 3 4 5 6 7 8 9 10 11 33 32 31 30 29 28 27 26 25 24 23 12 13 14 15 16 17 18 19 20 21 22 pa3 pa2 pa1 pa0 rd/e/ds ad0/a0 ad1/a1 ad2/a2 ad3/a3 ad4/a4 ad5/a5 pb5 pb6 pb7 reset wr/v pp or r/w bhe/psen v c c a19/csi pc2 pc1 pc0 44 43 42 41 40 39 38 37 36 35 34 (t op view)
2-109 o single chip programmable peripheral for microcontroller-based applications o 3.0 to 5.5 volt operation o 19 individually configurable i/o pins that can be used as: ? microcontroller i/o port expansion ? programmable address decoder (pad) i/o ? latched address output ? open drain or cmos o two programmable arrays (pad a & pad b) ? total of 40 product terms and up to 16 inputs and 24 outputs ? direct address decoding up to 1 meg address space and up to 16 meg with paging ?logic replacement o ?o glue?microcontroller chip-set ? built-in address latches for multiplexed address/data bus ? non-multiplexed address/data bus mode ? 8-bit data bus width ? ale polarity programmable ? selectable modes for read and write control bus as rd/wr, r/w/e, or r/w/ds ? psen pin for 8051 users o built-in page logic ? to expand the address space of microcontrollers with limited address space capabilities ? up to 16 pages o 512 kbits of uv eprom ? configured as 64k x 8 ? divides into 8 equal mappable blocks for optimized mapping ? block resolution is 8k x 8 ? 150 ns eprom access time, including input latches and pad address decoding. o 16 kbit static ram ? configured as 2k x 8 ? 150 ns sram access time, including input latches and pad address decoding o address/data track mode ? enables easy interface to shared resources (e.g., mail box sram) with other microcontrollers or a host processor o cmiser-bit ? programmable option to further reduce power consumption o built-in security ? locks the psd312l and pad decoding configuration o available in a choice of packages ? 44 pin pldcc, cldcc and tqfp o simple menu-driven software: configure the psd312l on an ibm pc o pin and functionally compatible with the psd3xx and psd3xxl series. key features programmable peripheral psd312l 3-volt single-chip microcontroller peripheral
psd3xx family 2-110 44-pin 44-pin pin name pldcc/cldcc tqfp package package psen 1 39 wr/v pp or r/w 2 40 reset 3 41 pb7 4 42 pb6 5 43 pb5 6 44 pb4 7 1 pb3 8 2 pb2 9 3 pb1 10 4 pb0 11 5 gnd 12 6 ale or as 13 7 p a7 14 8 p a6 15 9 p a5 16 10 p a4 17 11 p a3 18 12 p a2 19 13 p a1 20 14 p a0 21 15 rd/e/ds 22 16 ad0/a0 23 17 ad1/a1 24 18 ad2/a2 25 19 ad3/a3 26 20 ad4/a4 27 21 ad5/a5 28 22 ad6/a6 29 23 ad7/a7 30 24 a8 31 25 a9 32 26 a10 33 27 gnd 34 28 a11 35 29 a12 36 30 a13 37 31 a14 38 32 a15 39 33 pc0 40 34 pc1 41 35 pc2 42 36 a19/csi 43 37 v cc 44 38 psd312l pin assignments
psd3xx family 2-111 figur e 77. drawing j2 44-pin plastic leaded chip car rier (pldcc) (package t ype j) 39 a15 38 a14 37 a13 36 a12 35 a11 34 gnd 33 a10 32 a9 31 a8 30 ad7/a7 29 ad6/a6 pb4 7 pb3 8 pb2 9 pb1 10 pb0 11 gnd 12 ale or as 13 pa7 14 pa6 15 pa5 16 pa4 17 pa3 18 pa2 19 pa1 20 pa0 21 rd/e/ds 22 ad0/a0 23 ad1/a1 24 ad2/a2 25 ad3/a3 26 ad4/a4 27 ad5/a5 28 6 pb5 5 pb6 4 pb7 3 reset 2 wr/v or r/w 1 psen 44 v 43 a19/csi 42 pc2 41 pc1 40 pc0 pp cc 39 a15 38 a14 37 a13 36 a12 35 a11 34 gnd 33 a10 32 a9 31 a8 30 ad7/a7 29 ad6/a6 pb4 7 pb3 8 pb2 9 pb1 10 pb0 11 gnd 12 ale or as 13 pa7 14 pa6 15 pa5 16 pa4 17 pa3 18 pa2 19 pa1 20 pa0 21 rd/e/ds 22 ad0/a0 23 ad1/a1 24 ad2/a2 25 ad3/a3 26 ad4/a4 27 ad5/a5 28 6 pb5 5 pb6 4 pb7 3 reset 2 wr/v or r/w 1 psen 44 v 43 a19/csi 42 pc2 41 pc1 40 pc0 pp cc (t op view) (t op view) psd312l package infor mation figur e 76. drawing l4 44 pin ceramic leaded chip car rier (cldcc) with w indow (package t ype l)
psd3xx family 2-112 psd312l package infor mation figur e 78. drawing u1 44 pin plastic thin quad flatpack (tqfp) (package t ype u) pb4 pb3 pb2 pb1 pb0 gnd ale or as pa7 pa6 pa5 pa4 a15 a14 a13 a12 a11 gnd a10 a9 a8 ad7/a7 ad6/a6 1 2 3 4 5 6 7 8 9 10 11 33 32 31 30 29 28 27 26 25 24 23 12 13 14 15 16 17 18 19 20 21 22 pa3 pa2 pa1 pa0 rd/e/ds ad0/a0 ad1/a1 ad2/a2 ad3/a3 ad4/a4 ad5/a5 pb5 pb6 pb7 reset wr/v pp or r/w psen v c c a19/csi pc2 pc1 pc0 44 43 42 41 40 39 38 37 36 35 34 (t op view)
2-113 o single chip programmable peripheral for microcontroller-based applications o 3.0 to 5.5 volt operation o 19 individually configurable i/o pins that can be used as: ? microcontroller i/o port expansion ? programmable address decoder (pad) i/o ? latched address output ? open drain or cmos o two programmable arrays (pad a & pad b) ? total of 40 product terms and up to 16 inputs and 24 outputs ? direct address decoding up to 1 meg address space and up to 16 meg with paging ?logic replacement o ?o glue?microcontroller chip-set ? built-in address latches for multiplexed address/data bus ? non-multiplexed address/data bus mode ? selectable 8 or 16 bit data bus width ? ale polarity programmable ? selectable modes for read and write control bus as rd/wr, r/w/e, or r/w/ds ? bhe pin for byte select in 16-bit mode ? psen pin for 8051 users o built-in page logic ? to expand the address space of microcontrollers with limited address space capabilities ? up to 16 pages o 1m bit of uv eprom ? configurable as 128k x 8 or as 64k x 16 ? divides into 8 equal mappable blocks for optimized mapping ? block resolution is 16k x 8 or 8k x 16 ? 150 ns eprom access time, including input latches and pad address decoding. o 16 kbit static ram ? configurable as 2k x 8 or as 1k x 16 ? 150 ns sram access time, including input latches and pad address decoding o address/data track mode ? enables easy interface to shared resources (e.g., mail box sram) with other microcontrollers or a host processor o cmiser-bit ? programmable option to further reduce power consumption o built-in security ? locks the psd303l and pad decoding configuration o available in a choice of packages ? 44 pin pldcc, cldcc and tqfp o simple menu-driven software: configure the psd303l on an ibm pc o pin and functionally compatible with the psd3xx and psd3xxl series key features programmable peripheral psd303l 3-volt single-chip microcontroller peripheral
psd3xx family 2-114 44-pin 44-pin pin name pldcc/cldcc tqfp package package bhe/psen 1 39 wr/v pp or r/w 2 40 reset 3 41 pb7 4 42 pb6 5 43 pb5 6 44 pb4 7 1 pb3 8 2 pb2 9 3 pb1 10 4 pb0 11 5 gnd 12 6 ale or as 13 7 p a7 14 8 p a6 15 9 p a5 16 10 p a4 17 11 p a3 18 12 p a2 19 13 p a1 20 14 p a0 21 15 rd/e/ds 22 16 ad0/a0 23 17 ad1/a1 24 18 ad2/a2 25 19 ad3/a3 26 20 ad4/a4 27 21 ad5/a5 28 22 ad6/a6 29 23 ad7/a7 30 24 ad8/a8 31 25 ad9/a9 32 26 ad10/a10 33 27 gnd 34 28 ad11/a11 35 29 ad12/a12 36 30 ad13/a13 37 31 ad14/a14 38 32 ad15/a15 39 33 pc0 40 34 pc1 41 35 pc2 42 36 a19/csi 43 37 v cc 44 38 psd303l pin assignments
psdxx family 2-115 figur e 80. drawing j2 44 pin plastic leaded chip car rier (pldcc) (package t ype j) 39 ad15/a15 38 ad/14/a14 37 ad13/a13 36 ad12/a12 35 ad11/a11 34 gnd 33 ad10/a10 32 ad9/a9 31 ad8/a8 30 ad7/a7 29 ad6/a6 pb4 7 pb3 8 pb2 9 pb1 10 pb0 11 gnd 12 ale or as 13 pa7 14 pa6 15 pa5 16 pa4 17 pa3 18 pa2 19 pa1 20 pa0 21 rd/e/ds 22 ad0/a0 23 ad1/a1 24 ad2/a2 25 ad3/a3 26 ad4/a4 27 ad5/a5 28 6 pb5 5 pb6 4 pb7 3 reset 2 wr/v or r/w 1 bhe/psen 44 v 43 a19/csi 42 pc2 41 pc1 40 pc0 pp cc 39 ad15/a15 38 ad14/a14 37 ad13/a13 36 ad12/a12 35 ad11/a11 34 gnd 33 ad10/a10 32 ad9/a9 31 ad8/a8 30 ad7/a7 29 ad6/a6 pb4 7 pb3 8 pb2 9 pb1 10 pb0 11 gnd 12 ale or as 13 pa7 14 pa6 15 pa5 16 pa4 17 pa3 18 pa2 19 pa1 20 pa0 21 rd/e/ds 22 ad0/a0 23 ad1/a1 24 ad2/a2 25 ad3/a3 26 ad4/a4 27 ad5/a5 28 6 pb5 5 pb6 4 pb7 3 reset 2 wr/v or r/w 1 bhe/psen 44 v 43 a19/csi 42 pc2 41 pc1 40 pc0 pp cc (t op view) (t op view) psd303l package infor mation figur e 79. drawing l4 44 pin ceramic leaded chip car rier (cldcc) with w indow (package t ype l)
psd3xx family 2-116 psd303l package infor mation figur e 81. drawing u1 44 pin plastic thin quad flatpack (tqfp) (package t ype u) pb4 pb3 pb2 pb1 pb0 gnd ale or as pa7 pa6 pa5 pa4 ad15/a15 ad14/a14 ad13/a13 ad12/a12 ad11/a11 gnd ad10/a10 ad9/a9 ad8/a8 ad7/a7 ad6/a6 1 2 3 4 5 6 7 8 9 10 11 33 32 31 30 29 28 27 26 25 24 23 12 13 14 15 16 17 18 19 20 21 22 pa3 pa2 pa1 pa0 rd/e/ds ad0/a0 ad1/a1 ad2/a2 ad3/a3 ad4/a4 ad5/a5 pb5 pb6 pb7 reset wr/v pp or r/w bhe/psen v c c a19/csi pc2 pc1 pc0 44 43 42 41 40 39 38 37 36 35 34 (t op view)
2-117 o single chip programmable peripheral for microcontroller-based applications o 3.0 to 5.5 volt operation o 19 individually configurable i/o pins that can be used as: ? microcontroller i/o port expansion ? programmable address decoder (pad) i/o ? latched address output ? open drain or cmos o two programmable arrays (pad a & pad b) ? total of 40 product terms and up to 16 inputs and 24 outputs ? direct address decoding up to 1 meg address space and up to 16 meg with paging ?logic replacement o ?o glue?microcontroller chip-set ? built-in address latches for multiplexed address/data bus ? non-multiplexed address/data bus mode ? 8-bit data bus width ? ale polarity programmable ? selectable modes for read and write control bus as rd/wr, r/w/e, or r/w/ds ? psen pin for 8051 users o built-in page logic ? to expand the address space of microcontrollers with limited address space capabilities ? up to 16 pages o 1m bit of uv eprom ? configurable as 128k x 8 ? divides into 8 equal mappable blocks for optimized mapping ? block resolution is 16k x 8 ? 150 ns eprom access time, including input latches and pad address decoding. o 16 kbit static ram ? configurable as 2k x 8 ? 150 ns sram access time, including input latches and pad address decoding o address/data track mode ? enables easy interface to shared resources (e.g., mail box sram) with other microcontrollers or a host processor o cmiser-bit ? programmable option to further reduce power consumption o built-in security ? locks the psd313l and pad decoding configuration o available in a choice of packages ? 44 pin pldcc, cldcc and tqfp o simple menu-driven software: configure the psd313l on an ibm pc o pin and functionally compatible with the psd3xx and psd3xxl series key features programmable peripheral psd313l 3-volt single-chip microcontroller peripheral
psd3xx family 2-118 44-pin 44-pin pin name pldcc/cldcc tqfp package package psen 1 39 wr/v pp or r/w 2 40 reset 3 41 pb7 4 42 pb6 5 43 pb5 6 44 pb4 7 1 pb3 8 2 pb2 9 3 pb1 10 4 pb0 11 5 gnd 12 6 ale or as 13 7 p a7 14 8 p a6 15 9 p a5 16 10 p a4 17 11 p a3 18 12 p a2 19 13 p a1 20 14 p a0 21 15 rd/e/ds 22 16 ad0/a0 23 17 ad1/a1 24 18 ad2/a2 25 19 ad3/a3 26 20 ad4/a4 27 21 ad5/a5 28 22 ad6/a6 29 23 ad7/a7 30 24 a8 31 25 a9 32 26 a10 33 27 gnd 34 28 a11 35 29 a12 36 30 a13 37 31 a14 38 32 a15 39 33 pc0 40 34 pc1 41 35 pc2 42 36 a19/csi 43 37 v cc 44 38 psd313l pin assignments
psd3xx family 2-119 figur e 83. drawing j2 44-pin plastic leaded chip car rier (pldcc) (package t ype j) 39 a15 38 a14 37 a13 36 a12 35 a11 34 gnd 33 a10 32 a9 31 a8 30 ad7/a7 29 ad6/a6 pb4 7 pb3 8 pb2 9 pb1 10 pb0 11 gnd 12 ale or as 13 pa7 14 pa6 15 pa5 16 pa4 17 pa3 18 pa2 19 pa1 20 pa0 21 rd/e/ds 22 ad0/a0 23 ad1/a1 24 ad2/a2 25 ad3/a3 26 ad4/a4 27 ad5/a5 28 6 pb5 5 pb6 4 pb7 3 reset 2 wr/v or r/w 1 psen 44 v 43 a19/csi 42 pc2 41 pc1 40 pc0 pp cc 39 a15 38 a14 37 a13 36 a12 35 a11 34 gnd 33 a10 32 a9 31 a8 30 ad7/a7 29 ad6/a6 pb4 7 pb3 8 pb2 9 pb1 10 pb0 11 gnd 12 ale or as 13 pa7 14 pa6 15 pa5 16 pa4 17 pa3 18 pa2 19 pa1 20 pa0 21 rd/e/ds 22 ad0/a0 23 ad1/a1 24 ad2/a2 25 ad3/a3 26 ad4/a4 27 ad5/a5 28 6 pb5 5 pb6 4 pb7 3 reset 2 wr/v or r/w 1 psen 44 v 43 a19/csi 42 pc2 41 pc1 40 pc0 pp cc (t op view) (t op view) psd313l package infor mation figur e 82. drawing l4 44 pin ceramic leaded chip car rier (cldcc) with w indow (package t ype l)
psd3xx family 2-120 psd313l package infor mation figur e 84. drawing u1 44 pin plastic thin quad flatpack (tqfp) (package t ype u) pb4 pb3 pb2 pb1 pb0 gnd ale or as pa7 pa6 pa5 pa4 a15 a14 a13 a12 a11 gnd a10 a9 a8 ad7/a7 ad6/a6 1 2 3 4 5 6 7 8 9 10 11 33 32 31 30 29 28 27 26 25 24 23 12 13 14 15 16 17 18 19 20 21 22 pa3 pa2 pa1 pa0 rd/e/ds ad0/a0 ad1/a1 ad2/a2 ad3/a3 ad4/a4 ad5/a5 pb5 pb6 pb7 reset wr/v pp or r/w psen v c c a19/csi pc2 pc1 pc0 44 43 42 41 40 39 38 37 36 35 34 (t op view)
2-121 o single chip programmable peripheral for microcontroller-based applications o 3.0 to 5.5 volt operation o 19 individually configurable i/o pins that can be used as: ? microcontroller i/o port expansion ? programmable address decoder (pad) i/o ? latched address output ? open drain or cmos o two programmable arrays (pad a & pad b) ? total of 40 product terms and up to 16 inputs and 24 outputs ? direct address decoding up to 1 meg address space and up to 16 meg with paging ?logic replacement o ?o glue?microcontroller chip-set ? built-in address latches for multiplexed address/data bus ? non-multiplexed address/data bus mode ? selectable 8 or 16 bit data bus width ? ale polarity programmable ? selectable modes for read and write control bus as rd/wr, r/w/e, or r/w/ds ? bhe pin for byte select in 16-bit mode ? psen pin for 8051 users o built-in page logic ? to expand the address space of microcontrollers with limited address space capabilities ? up to 16 pages o 2m bit of uv eprom ? configurable as 256k x 8 or as 128k x 16 ? divides into 8 equal mappable blocks for optimized mapping ? block resolution is 32k x 8 or 16k x 16 ? 300 ns eprom access time, including input latches and pad address decoding. o address/data track mode ? enables easy interface to shared resources (e.g., mail box sram) with other microcontrollers or a host processor o cmiser-bit ? programmable option to further reduce power consumption o built-in security ? locks the psd304rl and pad decoding configuration o available in a choice of packages ? 44 pin pldcc, cldcc and tqfp o simple menu-driven software: configure the psd304rl on an ibm pc o pin and functionally compatible with the psd3xx and psd3xxl series key features programmable peripheral psd304rl 3-volt single-chip microcontroller peripheral
psd3xx family 2-122 44-pin 44-pin pin name pldcc/cldcc tqfp package package bhe/psen 1 39 wr/v pp or r/w 2 40 reset 3 41 pb7 4 42 pb6 5 43 pb5 6 44 pb4 7 1 pb3 8 2 pb2 9 3 pb1 10 4 pb0 11 5 gnd 12 6 ale or as 13 7 p a7 14 8 p a6 15 9 p a5 16 10 p a4 17 11 p a3 18 12 p a2 19 13 p a1 20 14 p a0 21 15 rd/e/ds 22 16 ad0/a0 23 17 ad1/a1 24 18 ad2/a2 25 19 ad3/a3 26 20 ad4/a4 27 21 ad5/a5 28 22 ad6/a6 29 23 ad7/a7 30 24 ad8/a8 31 25 ad9/a9 32 26 ad10/a10 33 27 gnd 34 28 ad11/a11 35 29 ad12/a12 36 30 ad13/a13 37 31 ad14/a14 38 32 ad15/a15 39 33 pc0 40 34 pc1 41 35 pc2 42 36 a19/csi 43 37 v cc 44 38 psd304rl pin assignments
psd3xx family 2-123 figur e 86. drawing j2 44 pin plastic leaded chip car rier (pldcc) (package t ype j) 39 ad15/a15 38 ad/14/a14 37 ad13/a13 36 ad12/a12 35 ad11/a11 34 gnd 33 ad10/a10 32 ad9/a9 31 ad8/a8 30 ad7/a7 29 ad6/a6 pb4 7 pb3 8 pb2 9 pb1 10 pb0 11 gnd 12 ale or as 13 pa7 14 pa6 15 pa5 16 pa4 17 pa3 18 pa2 19 pa1 20 pa0 21 rd/e/ds 22 ad0/a0 23 ad1/a1 24 ad2/a2 25 ad3/a3 26 ad4/a4 27 ad5/a5 28 6 pb5 5 pb6 4 pb7 3 reset 2 wr/v or r/w 1 bhe/psen 44 v 43 a19/csi 42 pc2 41 pc1 40 pc0 pp cc 39 ad15/a15 38 ad14/a14 37 ad13/a13 36 ad12/a12 35 ad11/a11 34 gnd 33 ad10/a10 32 ad9/a9 31 ad8/a8 30 ad7/a7 29 ad6/a6 pb4 7 pb3 8 pb2 9 pb1 10 pb0 11 gnd 12 ale or as 13 pa7 14 pa6 15 pa5 16 pa4 17 pa3 18 pa2 19 pa1 20 pa0 21 rd/e/ds 22 ad0/a0 23 ad1/a1 24 ad2/a2 25 ad3/a3 26 ad4/a4 27 ad5/a5 28 6 pb5 5 pb6 4 pb7 3 reset 2 wr/v or r/w 1 bhe/psen 44 v 43 a19/csi 42 pc2 41 pc1 40 pc0 pp cc (t op view) (t op view) psd304rl package infor mation figur e 85. drawing l4 44 pin ceramic leaded chip car rier (cldcc) with w indow (package t ype l)
psd3xx family 2-124 psd304rl package infor mation figur e 87. drawing u1 44 pin plastic thin quad flatpack (tqfp) (package t ype u) pb4 pb3 pb2 pb1 pb0 gnd ale or as pa7 pa6 pa5 pa4 ad15/a15 ad14/a14 ad13/a13 ad12/a12 ad11/a11 gnd ad10/a10 ad9/a9 ad8/a8 ad7/a7 ad6/a6 1 2 3 4 5 6 7 8 9 10 11 33 32 31 30 29 28 27 26 25 24 23 12 13 14 15 16 17 18 19 20 21 22 pa3 pa2 pa1 pa0 rd/e/ds ad0/a0 ad1/a1 ad2/a2 ad3/a3 ad4/a4 ad5/a5 pb5 pb6 pb7 reset wr/v pp or r/w bhe/psen v c c a19/csi pc2 pc1 pc0 44 43 42 41 40 39 38 37 36 35 34 (t op view)
2-125 o single chip programmable peripheral for microcontroller-based applications o 3.0 to 5.5 volt operation o 19 individually configurable i/o pins that can be used as: ? microcontroller i/o port expansion ? programmable address decoder (pad) i/o ? latched address output ? open drain or cmos o two programmable arrays (pad a & pad b) ? total of 40 product terms and up to 16 inputs and 24 outputs ? direct address decoding up to 1 meg address space and up to 16 meg with paging ?logic replacement o ?o glue?microcontroller chip-set ? built-in address latches for multiplexed address/data bus ? non-multiplexed address/data bus mode ? 8-bit data bus width ? ale polarity programmable ? selectable modes for read and write control bus as rd/wr, r/w/e, or r/w/ds ? psen pin for 8051 users o built-in page logic ? to expand the address space of microcontrollers with limited address space capabilities ? up to 16 pages o 2m bit of uv eprom ? configurable as 256k x 8 ? divides into 8 equal mappable blocks for optimized mapping ? block resolution is 32k x 8 ? 300 ns eprom access time, including input latches and pad address decoding. o address/data track mode ? enables easy interface to shared resources (e.g., mail box sram) with other microcontrollers or a host processor o cmiser-bit ? programmable option to further reduce power consumption o built-in security ? locks the psd314rl and pad decoding configuration o available in a choice of packages ? 44 pin pldcc, cldcc and tqfp o simple menu-driven software: configure the psd314rl on an ibm pc o pin and functionally compatible with the psd3xx and psd3xxl series key features programmable peripheral psd314rl 3-volt single-chip microcontroller peripheral
psd3xx family 2-126 44-pin 44-pin pin name pldcc/cldcc tqfp package package psen 1 39 wr/v pp or r/w 2 40 reset 3 41 pb7 4 42 pb6 5 43 pb5 6 44 pb4 7 1 pb3 8 2 pb2 9 3 pb1 10 4 pb0 11 5 gnd 12 6 ale or as 13 7 p a7 14 8 p a6 15 9 p a5 16 10 p a4 17 11 p a3 18 12 p a2 19 13 p a1 20 14 p a0 21 15 rd/e/ds 22 16 ad0/a0 23 17 ad1/a1 24 18 ad2/a2 25 19 ad3/a3 26 20 ad4/a4 27 21 ad5/a5 28 22 ad6/a6 29 23 ad7/a7 30 24 a8 31 25 a9 32 26 a10 33 27 gnd 34 28 a11 35 29 a12 36 30 a13 37 31 a14 38 32 a15 39 33 pc0 40 34 pc1 41 35 pc2 42 36 a19/csi 43 37 v cc 44 38 psd314rl pin assignments
psd3xx family 2-127 figur e 89. drawing j2 44-pin plastic leaded chip car rier (pldcc) (package t ype j) 39 a15 38 a14 37 a13 36 a12 35 a11 34 gnd 33 a10 32 a9 31 a8 30 ad7/a7 29 ad6/a6 pb4 7 pb3 8 pb2 9 pb1 10 pb0 11 gnd 12 ale or as 13 pa7 14 pa6 15 pa5 16 pa4 17 pa3 18 pa2 19 pa1 20 pa0 21 rd/e/ds 22 ad0/a0 23 ad1/a1 24 ad2/a2 25 ad3/a3 26 ad4/a4 27 ad5/a5 28 6 pb5 5 pb6 4 pb7 3 reset 2 wr/v or r/w 1 psen 44 v 43 a19/csi 42 pc2 41 pc1 40 pc0 pp cc 39 a15 38 a14 37 a13 36 a12 35 a11 34 gnd 33 a10 32 a9 31 a8 30 ad7/a7 29 ad6/a6 pb4 7 pb3 8 pb2 9 pb1 10 pb0 11 gnd 12 ale or as 13 pa7 14 pa6 15 pa5 16 pa4 17 pa3 18 pa2 19 pa1 20 pa0 21 rd/e/ds 22 ad0/a0 23 ad1/a1 24 ad2/a2 25 ad3/a3 26 ad4/a4 27 ad5/a5 28 6 pb5 5 pb6 4 pb7 3 reset 2 wr/v or r/w 1 psen 44 v 43 a19/csi 42 pc2 41 pc1 40 pc0 pp cc (t op view) (t op view) psd314rl package infor mation figur e 88. drawing l4 44 pin ceramic leaded chip car rier (cldcc) with w indow (package t ype l)
psd3xx family 2-128 psd314rl package infor mation figur e 90. drawing u1 44 pin plastic thin quad flatpack (tqfp) (package t ype u) pb4 pb3 pb2 pb1 pb0 gnd ale or as pa7 pa6 pa5 pa4 a15 a14 a13 a12 a11 gnd a10 a9 a8 ad7/a7 ad6/a6 1 2 3 4 5 6 7 8 9 10 11 33 32 31 30 29 28 27 26 25 24 23 12 13 14 15 16 17 18 19 20 21 22 pa3 pa2 pa1 pa0 rd/e/ds ad0/a0 ad1/a1 ad2/a2 ad3/a3 ad4/a4 ad5/a5 pb5 pb6 pb7 reset wr/v pp or r/w psen v c c a19/csi pc2 pc1 pc0 44 43 42 41 40 39 38 37 36 35 34 (t op view) psd3xx pr oduct or dering infor mation psd3xx f amily de vices are a v ailab le in a wide r ange of product selections . options and combinations include: architecture speed (access time) memor y siz e configur ation sram/no sram mask prog r ammability oper ating t emper ature range supply v oltages p ac kages please contact y our local wsi sales representativ e or distr ib utor f or the psd3xx product selection that best fits y our application and objectiv es .

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